JPS55150181A - Information processor - Google Patents

Information processor

Info

Publication number
JPS55150181A
JPS55150181A JP5798079A JP5798079A JPS55150181A JP S55150181 A JPS55150181 A JP S55150181A JP 5798079 A JP5798079 A JP 5798079A JP 5798079 A JP5798079 A JP 5798079A JP S55150181 A JPS55150181 A JP S55150181A
Authority
JP
Japan
Prior art keywords
directory
write request
dissidence
converted
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5798079A
Other languages
Japanese (ja)
Inventor
Toru Akai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5798079A priority Critical patent/JPS55150181A/en
Publication of JPS55150181A publication Critical patent/JPS55150181A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To increase the processing rate of a multiprocessor system by converting a partial write request into an entire write request without causing a data dissidence between a main memory and buffer memory.
CONSTITUTION: Processor 1, etc., is applied with an address correcponding to a partial write request and when it agrees with the contents of directory ADI1 stored with addresses of buffer memory MB1 of processor 1, the request couples with read data of memory MB1 at the address position and is converted into an entire write request. Further directory AD21 similar to directory ADI1 of controller 3 is compared with directory AD22 similar to directory AD12 of another processor 2 and when their coincidence is detected, the address of directory AD22 is invalidated and when the dissidence to directory AD21 is detected, the converted entire write request is returned, so that the partial write request will be converted into the entire write request high in processing speed without causing dissidence between common main memories 4 and 5 and memories MB1 and MB2.
COPYRIGHT: (C)1980,JPO&Japio
JP5798079A 1979-05-14 1979-05-14 Information processor Pending JPS55150181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5798079A JPS55150181A (en) 1979-05-14 1979-05-14 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5798079A JPS55150181A (en) 1979-05-14 1979-05-14 Information processor

Publications (1)

Publication Number Publication Date
JPS55150181A true JPS55150181A (en) 1980-11-21

Family

ID=13071150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5798079A Pending JPS55150181A (en) 1979-05-14 1979-05-14 Information processor

Country Status (1)

Country Link
JP (1) JPS55150181A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02207352A (en) * 1989-02-03 1990-08-17 Digital Equip Corp <Dec> Method and apparatus for interfacing system controller of multiprocessor system having central processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02207352A (en) * 1989-02-03 1990-08-17 Digital Equip Corp <Dec> Method and apparatus for interfacing system controller of multiprocessor system having central processor

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