JPS57167187A - Information processor - Google Patents

Information processor

Info

Publication number
JPS57167187A
JPS57167187A JP56051163A JP5116381A JPS57167187A JP S57167187 A JPS57167187 A JP S57167187A JP 56051163 A JP56051163 A JP 56051163A JP 5116381 A JP5116381 A JP 5116381A JP S57167187 A JPS57167187 A JP S57167187A
Authority
JP
Japan
Prior art keywords
reading
writing
coincidence
data
cms
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56051163A
Other languages
Japanese (ja)
Inventor
Akira Jitsupou
Yuzo Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56051163A priority Critical patent/JPS57167187A/en
Publication of JPS57167187A publication Critical patent/JPS57167187A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To realize the reading of data out of the cash memory while the block is transferred and to another subsequent data reading request, by providing two split cash memories plus a specific detecting means, indicating means, etc. CONSTITUTION:A cash memory consists of two split memories (CM) 2 and 3 which are capable of the writing and reading independently of each other. A detecting means 8 is provided to detect whether the coincidence exists between the writing CM and the reading CM or not. The means 9 and 10 supply the writing and reading addresses to the CMs 2 and 3 when no coincidence is detected by the means 8, indicate to perform the parallel writing and reading actions to the CM2 and 3, and furthermore indicate to carry out the reading process for the reading CM in preference to the writing process of the writing CM in case when the coincidence is obtained in the detection of the means 8. And a writing data storing buffer 4 stores the data which is written into the CMs 2 and 3 from a storage device 1.
JP56051163A 1981-04-07 1981-04-07 Information processor Pending JPS57167187A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56051163A JPS57167187A (en) 1981-04-07 1981-04-07 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56051163A JPS57167187A (en) 1981-04-07 1981-04-07 Information processor

Publications (1)

Publication Number Publication Date
JPS57167187A true JPS57167187A (en) 1982-10-14

Family

ID=12879149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56051163A Pending JPS57167187A (en) 1981-04-07 1981-04-07 Information processor

Country Status (1)

Country Link
JP (1) JPS57167187A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01251247A (en) * 1988-02-22 1989-10-06 Internatl Business Mach Corp <Ibm> Cash memory subsystem

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01251247A (en) * 1988-02-22 1989-10-06 Internatl Business Mach Corp <Ibm> Cash memory subsystem

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