JPS6488672A - Multiprocessor system - Google Patents

Multiprocessor system

Info

Publication number
JPS6488672A
JPS6488672A JP62247194A JP24719487A JPS6488672A JP S6488672 A JPS6488672 A JP S6488672A JP 62247194 A JP62247194 A JP 62247194A JP 24719487 A JP24719487 A JP 24719487A JP S6488672 A JPS6488672 A JP S6488672A
Authority
JP
Japan
Prior art keywords
address
information
job
buffer memory
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62247194A
Other languages
Japanese (ja)
Inventor
Kazuhisa Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62247194A priority Critical patent/JPS6488672A/en
Publication of JPS6488672A publication Critical patent/JPS6488672A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To easily identify a job and to enhance the validity of a buffer memory by storing a part of the address of block unit information and the flag information of the job in order to instruct the block unit information held in the data part of an address array part. CONSTITUTION:At the time of having an access request to a buffer memory 1, the buffer memory 1 respectively receives the address information of desired data and the flag information of the job from an address register 5, a flag register 6, a part of the address information stored in the address array part 3 and the flag information are read from the address array part 3, supplied to an address comparator 4 and when both information coincides, the address comparator 4 transmits a presence signal 7. Thereby, after the job is temporarily interrupted, it is resumed and then, the job can be easily identified to enhance the validity of the buffer memory.
JP62247194A 1987-09-29 1987-09-29 Multiprocessor system Pending JPS6488672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62247194A JPS6488672A (en) 1987-09-29 1987-09-29 Multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62247194A JPS6488672A (en) 1987-09-29 1987-09-29 Multiprocessor system

Publications (1)

Publication Number Publication Date
JPS6488672A true JPS6488672A (en) 1989-04-03

Family

ID=17159845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62247194A Pending JPS6488672A (en) 1987-09-29 1987-09-29 Multiprocessor system

Country Status (1)

Country Link
JP (1) JPS6488672A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6079446A (en) * 1983-10-06 1985-05-07 Hitachi Ltd Processor for multiple virtual storage data

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6079446A (en) * 1983-10-06 1985-05-07 Hitachi Ltd Processor for multiple virtual storage data

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