JPS57143781A - Control system for storage device - Google Patents

Control system for storage device

Info

Publication number
JPS57143781A
JPS57143781A JP56028477A JP2847781A JPS57143781A JP S57143781 A JPS57143781 A JP S57143781A JP 56028477 A JP56028477 A JP 56028477A JP 2847781 A JP2847781 A JP 2847781A JP S57143781 A JPS57143781 A JP S57143781A
Authority
JP
Japan
Prior art keywords
storage device
block
request
circuit
buffer storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56028477A
Other languages
Japanese (ja)
Other versions
JPS6017134B2 (en
Inventor
Mitsushi Okabayashi
Tomoatsu Yanagida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56028477A priority Critical patent/JPS6017134B2/en
Publication of JPS57143781A publication Critical patent/JPS57143781A/en
Publication of JPS6017134B2 publication Critical patent/JPS6017134B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To prevent the occurrence of dissidence of the storaged content between a main storage device and a buffer storage device, by suppressing the registration of information to the buffer storage device, if write request of the same block of the main storage device takes place, while block information is transferred to the buffer storage device. CONSTITUTION:In outputting a block transfer request to a main storage device 35 via a block transfer request issuing logical circuit 315 of a buffer storage device 31, when a request reception section 311 receives the block rewrite request of the device 31, an address of the request of an address register 312 is compared with a block transfer address of a block transfer address register 316 at a comparison circuit 317. When both the addresses are coincident, an AND circuit 3192 is closed via a coincidence circuit 318 and a NAND circuit 3182, a block replace signal from a block transfer logical processing circuit 319 is interrupted and the registration from the device 35 to the device 31 is suppressed. Thus, the production of inconvenience such as dissidence of the storaged content between the main storage device and the buffer storage device is eliminated.
JP56028477A 1981-03-02 1981-03-02 Storage device control method Expired JPS6017134B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56028477A JPS6017134B2 (en) 1981-03-02 1981-03-02 Storage device control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56028477A JPS6017134B2 (en) 1981-03-02 1981-03-02 Storage device control method

Publications (2)

Publication Number Publication Date
JPS57143781A true JPS57143781A (en) 1982-09-06
JPS6017134B2 JPS6017134B2 (en) 1985-05-01

Family

ID=12249720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56028477A Expired JPS6017134B2 (en) 1981-03-02 1981-03-02 Storage device control method

Country Status (1)

Country Link
JP (1) JPS6017134B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154039A (en) * 1985-12-27 1987-07-09 Hitachi Ltd Buffer memory control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154039A (en) * 1985-12-27 1987-07-09 Hitachi Ltd Buffer memory control system

Also Published As

Publication number Publication date
JPS6017134B2 (en) 1985-05-01

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