JPS5771044A - Data buffer control system - Google Patents
Data buffer control systemInfo
- Publication number
- JPS5771044A JPS5771044A JP14782580A JP14782580A JPS5771044A JP S5771044 A JPS5771044 A JP S5771044A JP 14782580 A JP14782580 A JP 14782580A JP 14782580 A JP14782580 A JP 14782580A JP S5771044 A JPS5771044 A JP S5771044A
- Authority
- JP
- Japan
- Prior art keywords
- data
- byte
- same time
- read
- addresses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To eliminate the need for an aligning circuit for data, by generating transfer data starting addresses at an optional byte boundary in a control circuit for a data buffer wherein the transfer data is stored temporarily. CONSTITUTION:Write address registers WA0-WA1, a read address register RA, and (m) units of (n)-byte-width data buffers DB0-DB3 which can be accessed with mutually different at the same time are equipped. When (n)-byte data is written, the (n)-byte data is written in different addresses of the (m) buffer memories at the same time, and when (mXn)-byte data is read, the (mXn)-byte data is read from the same addresses of the (m) buffer memories at the same time. Therefore, transfer data starting at an optional type boundary is generated without providing a byte aligning means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14782580A JPS5771044A (en) | 1980-10-22 | 1980-10-22 | Data buffer control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14782580A JPS5771044A (en) | 1980-10-22 | 1980-10-22 | Data buffer control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5771044A true JPS5771044A (en) | 1982-05-01 |
Family
ID=15439077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14782580A Pending JPS5771044A (en) | 1980-10-22 | 1980-10-22 | Data buffer control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5771044A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0290172A2 (en) * | 1987-04-30 | 1988-11-09 | Advanced Micro Devices, Inc. | Bidirectional fifo with variable byte boundary and data path width change |
-
1980
- 1980-10-22 JP JP14782580A patent/JPS5771044A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0290172A2 (en) * | 1987-04-30 | 1988-11-09 | Advanced Micro Devices, Inc. | Bidirectional fifo with variable byte boundary and data path width change |
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