JPS57100680A - Page fault processing system - Google Patents

Page fault processing system

Info

Publication number
JPS57100680A
JPS57100680A JP55175863A JP17586380A JPS57100680A JP S57100680 A JPS57100680 A JP S57100680A JP 55175863 A JP55175863 A JP 55175863A JP 17586380 A JP17586380 A JP 17586380A JP S57100680 A JPS57100680 A JP S57100680A
Authority
JP
Japan
Prior art keywords
page fault
instruction
address
writing operation
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55175863A
Other languages
Japanese (ja)
Other versions
JPH0133856B2 (en
Inventor
Tadaaki Bando
Hidekazu Matsumoto
Yasushi Fukunaga
Yoshinari Hiraoka
Toshiyuki Ide
Tetsuya Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP55175863A priority Critical patent/JPS57100680A/en
Priority to US06/329,949 priority patent/US4520441A/en
Publication of JPS57100680A publication Critical patent/JPS57100680A/en
Publication of JPH0133856B2 publication Critical patent/JPH0133856B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To perform page fault processing at a high speed without increasing overhead, by storing the address of an instruction, etc., interrupted according to a page fault signal, in a store buffer temporarily and by handling it when the instruction is restarted. CONSTITUTION:Once a page fault occurs, the contents of an address register 26 are transferred to a store buffer 38, wherein the same contents as those written in a cash register consisting of a directory part 29 and a data part 30 in writing operation, temporarily according to an interruption instruction. Simultaneously, an interruption signal is generated and when page fault processing ends, reading operation is restarted by an instruction which corresponds to an address, etc., held in the buffer 38 temporarily. In case of an error page fault during writing operation, the address of a next instruction is stored in the buffer 38 after the writing operation ends and restarting processing is performed similarly. Therefore, the need to make an address check or to retain instruction input data before reading and writing operation is eliminated, and the page fault processing is performed at a high speed without increasing an overhead.
JP55175863A 1980-12-15 1980-12-15 Page fault processing system Granted JPS57100680A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP55175863A JPS57100680A (en) 1980-12-15 1980-12-15 Page fault processing system
US06/329,949 US4520441A (en) 1980-12-15 1981-12-11 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55175863A JPS57100680A (en) 1980-12-15 1980-12-15 Page fault processing system

Publications (2)

Publication Number Publication Date
JPS57100680A true JPS57100680A (en) 1982-06-22
JPH0133856B2 JPH0133856B2 (en) 1989-07-17

Family

ID=16003512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55175863A Granted JPS57100680A (en) 1980-12-15 1980-12-15 Page fault processing system

Country Status (1)

Country Link
JP (1) JPS57100680A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59152578A (en) * 1983-02-18 1984-08-31 Toshiba Corp Page fault processing system
JPS6255736A (en) * 1985-08-30 1987-03-11 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Digital processor control
JPS62143149A (en) * 1985-12-18 1987-06-26 Hitachi Ltd Memory managing unit for information processing system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2576594Y2 (en) * 1991-12-10 1998-07-16 東陶機器株式会社 Toilet door with emergency door

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5168733A (en) * 1974-12-11 1976-06-14 Fujitsu Ltd
JPS53121538A (en) * 1977-03-31 1978-10-24 Fujitsu Ltd Information processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5168733A (en) * 1974-12-11 1976-06-14 Fujitsu Ltd
JPS53121538A (en) * 1977-03-31 1978-10-24 Fujitsu Ltd Information processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59152578A (en) * 1983-02-18 1984-08-31 Toshiba Corp Page fault processing system
JPS6255736A (en) * 1985-08-30 1987-03-11 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Digital processor control
JPS62143149A (en) * 1985-12-18 1987-06-26 Hitachi Ltd Memory managing unit for information processing system

Also Published As

Publication number Publication date
JPH0133856B2 (en) 1989-07-17

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