JPS59152578A - Page fault processing system - Google Patents

Abstract

PURPOSE:To restart the operation from the instruction interrupted with an operating circuit, by providing the operating circuit and the first and the second registers and saving contents of the second register when a page fault occurs and restoring saved contents when the instruction is restarted. CONSTITUTION:When a page fault occurs during the memory read, contents of an unprocessed write data length storage register 39 are saved because the length of data to be written is stored in this register 39. When a page fault occurs during the memory write, contents of the register 39 are saved because the length of unprocessed write data just before the page fault is stored. The instruction restart due to the page fault is discriminated just after instruction fetch, and the restart processing micro routine of the instruction is exectued. It is unnecessary to check whether the page fault occurs before the execution of the instruction or not, and the execution of the instruction is restarted at the page fault occurrence time without the influence upon the execution time.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is based on hypothetical theory.1. Made of data processing that supports piles (
, - page-for-note processing applied to f4).

[Technical background of the invention and its problems] Consisting of the main memory of the small RI and the external memory of the Inu'yong Group 7.
A virtual memory system is a system that uses a physical structure to realize a logical structure consisting of a main memory with a huge amount of capacity that programmers can use as they wish. This is possible by taking advantage of the fact that during program execution, the entire program is not constantly and uniformly referenced, but only a portion of it is needed at each stage. The advantage is that only the parts that are likely to be referenced as the stages progress are replaced in the main memory.

In the data processing device that supports the above-mentioned virtual memory, page fault processing (interrupt processing when a table search is performed and the required address does not exist) when the address to be accessed does not exist in the main memory.
will be carried out. Among these processes, one that is particularly complex is the method of resuming instruction execution after a page fault. In other words, when a page fault occurs, it is only necessary to restart from the point at which it occurred, but for this purpose,
It is necessary to save the contents of various work registers and flip-flops that are about to be used by the hardware, load the page into main memory, and restore them when restarting. but,
Since there is a lot of such information and it varies depending on the model, there are many problems in adopting this method.

For this reason, the following methods are adopted for -ya against page faults.

The first method is to perform an address check before reading or writing to the memory, and execute the instruction after confirming that no page fault occurs. Although this method is simple, it has the disadvantage that an address check must be performed for each instruction in advance, which increases execution time.

The second method is to hold the input data of an instruction, and when a page fault occurs, restore this manual data to the original state when restarting. However, this method has the disadvantage of increasing the overhead of storing input data.

What both of the first and second methods have in common is that they have the desirable property that no page fault occurs (the second method also increases overhead).

The third method focuses on the flexibility that generally when an instruction is executed, various data are read from the memory first, and the interpolation is performed after 70, and adopts the method shown below. In other words, Day! During the reading 7 period (
When a two-page fault occurs, there is no change in the data input to the instruction, so the address of the instruction is saved, the page is loaded into main memory, and then the saved instruction is retried. , - 10,000, When a page fault occurs when writing data, the write data and write address are stored in a separate buffer memory, the page fault processing is performed after the instruction is completed, and when the instruction is restarted, , the stored data is also omitted at the write address stored in a separate buffer memory, and the instruction is restarted from the instruction following the interrupted instruction. FIG. 1 shows an overview of the instruction processing flow to which this method can be applied.

However, this method cannot be used when the instruction flow alternates between reading and writing, as shown in FIG. 2, and it is necessary to use the method shown in the first example.

Reading large amounts of data such as string processing/
Even in the case of a write instruction, in order to complete the instruction when a page fault occurs, a separate large-capacity buffer memory is required, which has the disadvantage of increasing the amount of hardware. In addition, when the capacity of the separate buffer memory is reduced, it is necessary to check whether a two-page fault occurs before executing a string processing instruction. It has the undesirable property of increasing overhead for string instructions.

[Purpose of the invention]

The present invention has been developed in consideration of the above-mentioned drawbacks, eliminates processing overhead, reduces the number of registers to be saved even when a page field occurs, and reduces the number of registers that need to be saved when restarting (2). An object of the present invention is to provide a page fault processing method that can restart an interrupted instruction from the middle without going through the steps.

[Summary of the Invention] The present invention is a data processing device (preferably employed) that supports virtual memory, and a first register whose value is updated by some amount of data to be processed every time a memory write command is executed. , an arithmetic circuit that performs a length operation based on the register output and the data length to be processed, and a second register that obtains data from the first register and is written (value is updated) by memory command execution f2. When a page 7 ort occurs, the contents of the second register are saved, and when the instruction is restarted, the saved contents are restored, the address and data length of the data to be restarted are calculated by the arithmetic circuit, and the interrupted instruction is The operation is restarted from the middle of the process.

By adopting the page fault processing method of the present invention, the various drawbacks mentioned above can be overcome.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail using FIG. 3 and subsequent figures.

FIG. 3 is a block diagram showing an embodiment of an apparatus for implementing the present invention.

In the figure, 31 is a selector. The selector 31 is given a "data length" to be set in length registers 32 and 33, which will be described later, from the outside via a line 301 at the beginning of microinstruction execution. The length register 3 is also provided via line 308.
2.33 stores the remaining READ data length to be processed and the remaining WRITE data length to be processed, respectively. 34 is a selector.

The selector 34 obtains the output of the register 32, s:a, and the microinstruction command is READ/W几I'T.
' Whichever E is specified, ζ2 outputs the contents of the corresponding register. That is, when the field f of R E A D with respect to the memory (not shown) is set, the length register 32 is
In the case of WRITE, the contents of the length register 33 are selectively output.

35 is also a selector. The selector 35 is externally supplied with the data length to be processed in the read/write/input microinstruction to the memory, and outputs the data for dialysis. 3
6 is a subtracter that performs length reduction. Subtractor 36
are supplied with the outputs of the selectors 34 and 35, and the line/
Length register 32 or 3 provided via 304
From the contents of 3, the ``data length (line 306)'' to be processed by the microinstruction is subtracted.

Reference numerals 37 and 38 designate flip-flops that display whether or not the value of the length registers 32 and 33 has become negative as a result of the length subtraction by the subtractor 36. Flip-flop 37, 38 output (line 3o 9/31o)
-f: Indicates that [ΔD/WRITE has finished, respectively.

In addition, length registers 32 and 33 (the second is READ/WR
The value from which the length is subtracted when the ITE command is executed is written via the selector 31.

39 is memory, command execution time (RgAD/WR, I
'l'E), data length register 33
This is an unprocessed write data length register that stores the contents of .

4th f! S4 is a diagram showing the flow of instructions to which the page fault processing 'J formula of the present invention is applied.

FIG. 5 is a block diagram showing another embodiment of the present invention.

In the figure, numeral 5 is a selector, 52 is a written data length register that zeros in when an instruction is fetched, and stores the output of the selector 51 (the bit value of line 502) when memory writing is executed. 53 is a selector that selects and outputs the data length to be processed by a write microinstruction to the memory; 54 is a write-in data length register 52 output (contents of line 503); This is an adder that adds and outputs the data length (contents of line 504). At the time of a memory write command, the selector 51 selects the data length addition result (line 5θ5
content) and selects and outputs the written data length register 2 and 3.
When writing the required data length to 2 (2 is line 50
Selectively output the contents of 1. 55 is memory command execution (
Second, it is a write-processed data length register for page faults that stores the contents of the register 32.

The operation of the embodiment shown in FIG. 3 will be explained below.

The length registers 32 and 33 are set to c, after the start of the microinstruction, and before executing the READ/WRI'l''E command to the memory (2:f:i''L, respectively the read data length,
The write data length is set redundantly. When the memo IJ kf import is executed, the selector 34 selects the length register 32, the selector 35 selects the data length to be read, and the subtractor 36 subtracts the input data (the contents of line 305). - the contents of line 306), and its output (the contents of line 3θ8) is written into the length register 32 via the selector 3. As a result, the length register 32 (= means read after this.

This means that the data length that needs to be filled is stored.

At this time, the unprocessed write data length storage register 3
9 stores the contents of the write data length register 33. Similarly, at the time of a memory write command, the contents of the write data length storage register 33 are subtracted. At this time,
The unprocessed write data length register 39 stores the (c) content of the write data length register 33 before the length is subtracted.

If a page fault occurs when reading memory, the unprocessed write data length storage register 39 (second
The data length to be written from now on is stored, and this content is saved.

Furthermore, when a page fault occurs during memory writing, the unprocessed write data length storage register 39 stores the unprocessed write data length immediately before the page fault occurs, and this content is saved. When the instruction is restarted after the page fault processing, immediately after fetching the instruction in the flow shown in FIG. In this microroutine, 402
Subtract the saved unprocessed write data length from the write data length before executing the instruction in step , calculate the processed data length, and subtract the unprocessed write data length from the read data length before executing the instruction. Calculate the read data length when restarting the instruction, and store this in the length register 32.
and store the unprocessed write data lengths in the length register 33, respectively.

In the Hata Uni microroutine 403, the read address and blue entry address at the time of restart are corrected based on the processed data length, and instruction processing is restarted.

In the embodiment shown in FIG. 5, when a page fault occurs due to memory command execution (2), the page fault written data length register, which stores the length of the written data before the execution of the command 7. The contents of the file are saved, page fault processing is performed, and the instruction is restarted.To restart, calculate the remaining read data length and write data length based on the processed data length that was saved, and read and write the write address. Correct the problem and resume processing instructions.

〔Effect of the invention〕

As explained above, the present invention has the following effects.

[11] There is no need to check whether a page fault occurs before executing an instruction, and instruction execution can be resumed when a page fault occurs without affecting execution time.

(2) There is less data to be saved, such as registers necessary for restarting instructions after page fault processing.

(3) There is no need to check whether a page 7 fault occurs even in cases where long data such as string processing instructions may be handled.

(4) It is possible to prevent the microprogram necessary for restarting an instruction after page fault processing from becoming complicated.

[Brief explanation of drawings]

1 and 2 are diagrams showing an overview of the processing flow of instructions to which the conventional page fault processing method can be applied, FIG. 3 is a block diagram showing an embodiment of a device that implements the present invention, and FIG. A diagram showing the flow of instructions to which the page fault processing method of the invention is applied, FIG. 5 is a block diagram showing another embodiment of the invention. 31, 34, ? 5, 51, 53...Zelector, 32, 33, 39, 52, 55...
Register, 36...subtractor, 54...adder. Applicant's agent Patent attorney Takehiko Suzue Figure 1
2nd Prisoner Figure 3 Figure 5':) (J') Figure 4

Claims (3)

[Claims] (1) Temporarily, 'l:'A g+', ・If you have a data processing device that supports tfi-C, when executing a memory command, there is a means to set and output the data length to be processed, and the above every time a memory write command is executed. The first data ('4': drawing means and the second data holding means) is updated by the data essential given by the means, and the length calculation is performed based on the data length to be processed. - a second data holding board that receives data from the first data acquisition means and is written in by executing a memory command; At the time of occurrence, the contents by the second data holding means are written in -.
il L,, when reading the command, use the above data to determine the address and data length of the data to be opened, and restart the command. Page Fault +111 Katana style, which is characterized by the following. (2) The above-mentioned first data holding means holds the data length of the memory write in some places, and the data length given by the above-mentioned setting output means is added, and the data length is updated for each memory writing command. The feature of the page fumeert treatment as set forth in claim 1 is as follows. (3) - The first data holding means (receiver) holds the unprocessed data length that needs to be filled into the memory, and holds the AiW-g for the amount of data given by the above-mentioned constant output means.
A page fault handling method according to claim 1, characterized in that the page fault handling method FJ75 is characterized in that a history is flushed every time a memory write command is executed.