JPS5890244A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the reading time of an instruction for a small-scale instruction loop, by reading the instruction directly out of an instruction buffer while the branching conditions of a branch are satisfied. CONSTITUTION:For a small-scale instruction loop formed by a specific instruction loop, an instruction loop is assumed with a specific branch instruction. Then a detecting circuit 15 is provided to check whether the instruction loop can enter an instruction buffer 2. If the instruction loop can enter the buffer 2, the reading of an extra instruction is inhibited so that the entire instruction included in the loop can be held within the buffer 2 while the loop is carrying out a process. This can eliminated a delay of process which is caused while the instruction given from a buffer memory 1 is read and then stored in the buffer 2 and with each branching.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to reading a branch destination instruction of a branch instruction using an instruction buffer, particularly for several instructions.

This is a so-called instruction loop in which 7 instructions are repeatedly executed.

The present invention relates to a data processing device suitable for small-scale applications.

Conventionally, in a branch instruction, the branch destination instruction is necessarily read from the memory to the instruction buffer to start processing the instruction. Therefore, in the case of a small-scale instruction loop that can fit into the instruction buffer, even though the instruction to be repeatedly executed has already been read into the instruction buffer, it is read out from memory again and the There is a drawback that reading time is required.

An object of the present invention is to distinguish a branch instruction that is often used when configuring a small-scale instruction loop Z from other branch instructions, and to reduce the instruction read time in a small-scale instruction loop using such a specific branch instruction. The goal is to shorten the time.

In a small-scale instruction loop, in order to shorten the time of directly reading instructions that have already been taken into the instruction buffer, or reading instructions from the backup memory, 1. Instruction loop with a specific branch instruction? Assuming that, the instruction loop checks whether the instruction buffer gets filled.

It has a built-in circuit and can loop within the instruction buffer.

If so, stop reading the extra instructions and include them in the loop.The entire instruction is placed in the instruction buffer 7 during loop processing.

We decided to use a method that allows it to be saved.

EMBODIMENT OF THE INVENTION Hereinafter, one example of the present invention will be explained with reference to the drawings.

1 is a buffer memory. This buffer 7 memory 1 is
Main memory J: has a small capacity and high speed, and program instructions are stored as a copy of the main memory.

In this embodiment, it is assumed that all instructions in the main memory are stored in the buffer memory 1, and the instruction length is 16 strings or 32 bits.

The read width of an instruction for one buffer memory is 64 bits. 2 is an instruction buffer. Instruction buffer 2 is 64
It consists of four bit registers. The command buffer 2 is the main memory and can hold up to 256 bits of consecutive command data.

Instruction read is a 64-bit request buffer 7 memo addressed by the instruction read address register 6°.

This is done by loading it into the instruction buffer 2 from the beginning.

Instructions other than branch instructions are executed sequentially in the main memory, so if one instruction read is completed and there is still space in the instruction buffer, the contents of the instruction read address register 6 are incremented by 1 by the Caro calculator 21. An instruction read request is made as the next instruction read address.

The instruction extraction circuit 3 transfers the desired instruction 7 from the instruction buffer 2 to the instruction register 4, left-justified. instruction register 4
takes in the extracted instruction and starts processing the instruction.

The instruction extraction register 7 holds the address in the instruction buffer 2 of the instruction extracted to the instruction register 4. The decoder 5 decodes the instruction length t from the instruction entered in the instruction register 4 and inputs it to the adder 8. The adder 8 adds the contents of the instruction extraction register and the instruction length 7, and outputs the start address of the next instruction extraction.

As explained above, the instruction M1 is normally addressed sequentially, including the instruction buffer 2 and the instruction register.

Transfer 7 to 4 is executed, but the branch instruction is executed.

If the condition holds true, the order of instruction reading j111 will be disrupted.

Here, the instruction loop 7 which is the subject of the present invention.

branch instruction (hereinafter referred to as loop instruction)
The following describes the processing.

The instruction counter 9 normally indicates the address of the instruction loaded into the instruction register 4.

When a loop instruction is taken into the instruction register 4, its branch destination address 7 is calculated by the address calculation circuit 11, and is input to the intervening loop detection circuit 15 via the address line 10, and the address of the loop instruction itself is also input via the address line 20. Manpower. The loop detection path 15 compares the two input addresses and performs a test 7 to determine whether the entire instruction loop can be entered into the instruction buffer 2.

This test allows a loop within instruction buffer 2.

If so, the flip-flop indicates that the loop instruction is being processed,
Z, 12Y1, and if flip-flop IJ12 is 0, flip-flop P13 indicates 7 in preparation for loop instruction.
shall be.

While the flip-flop L12 is at 1, updating of the instruction counter 9 is prohibited and the loop instruction address is held.

The branch destination address register 4 is a flip-flop Li.
2 is 0, and after the loop instruction enters the instruction register 4, the branch destination address is input, and the branch destination address is held while the flip-flop L12 is set to 1.

When the flip-flop L12 becomes 1, only instructions from the branch destination instruction to the loop instruction are read, and reading of instructions after the loop instruction is prohibited.

When all instructions requested to be read during loop instruction preparation have been read into instruction buffer 2, flip-flop P15 pin 0
The preparation for the loop instruction is completed. Branch detection circuit 16
Then, address line 19 is required and human power ″″f7. ;) An instruction counter that holds the instruction address and the instruction address of the loop instruction.

9 is constantly compared, and if they match, the loop instruction is taken into the instruction register 4.

The branch destination instruction (7) extraction address Z is input to the instruction extraction register 7 from the branch destination instruction address register 14. In the next cycle, the adder 8 goes to +0 and the branch destination instruction is extracted from the instruction buffer.

Thereafter, branching is continued in the same manner until the branching condition of the loop instruction is not satisfied. When the loop instruction is executed and the branch condition is not satisfied, flip-flop L12 and flip-flop P 1 ! , Y are both 0.

Instruction processing after the branch destination instruction that was assumed to be executed next to the loop instruction Jl! Y Disable.

The instruction read address register 6 includes a loop instruction 64
After the instruction read of the bit, the bit is incremented by 1 by the adder 21, and then the read address is indicated by 64 pits. Using this address, the instruction read 1ilt, 'Y is started and the operation returns to the current operation.

In addition, the instruction 'fW' in the instruction loop may be replaced by the instruction in the instruction loop, or the branch destination address of the loop instruction may be changed. .

In such a case, the loop instruction processing described above becomes impossible.

Therefore, the program store detection circuit 1B checks whether the instruction within the instruction loop has been rewritten, and the branch destination address comparison circuit 17 checks whether the branch destination address of the loop instruction has been changed.

The store address register 22 holds the address when the memory contents 7 are rewritten.

At the program store detection time [18], the address of the loop instruction is sent through the address N 20 Y, and the branch destination address of the loop instruction is sent through the address line 23.

Further, the address of the memory to be rewritten is input via the address line 24.

The program store detection circuit 18 detects when an instruction 'kVJ' in the section from the branch destination of the loop instruction to the loop instruction is to be replaced and requests rewriting. Processing after the next instruction is invalidated, flip-flop L12 and flip-flop P13'Y are both set to 0, and processing is restarted from reading the next instruction after performing one change.

The branch destination address comparison circuit 17 receives the branch destination address of the loop instruction taken in at the start of the loop instruction via the address line 23, and the branch destination address of the loop instruction is sent to the address line 23 each time the loop instruction is taken into the instruction register. It is input via M107.

The branch destination address comparison circuit 17 compares these two arrays and detects a mismatch. When the branch destination address comparison circuit 17 compares these two arrays and detects a mismatch, the flip-flop L12 and the flip-flop 70 turn P13.
and is processed as a branch instruction.

As described above, according to the present invention, in a small-scale instruction loop where a specific branch instruction in which a branch condition is frequently satisfied can be stored in a 5-instruction buffer, the buffer 7 memory that is generated each time the branch is Processing delay Z in the case from reading the instruction to storing it in the instruction buffer
It can be used without any problems and has the effect of improving performance.

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[Brief explanation of the drawing]

The figure is a block diagram showing a data processing device jltY according to the present invention. 2...Pa instruction buffer, 12...Flip-flop L. 13...Flip-flop P. 15...Loop detection circuit. 16... Branch detection circuit, 17... Branch destination address comparison circuit, 18... Program store detection circuit.

Claims (1)

[Claims] 1. Read and store multiple instructions from memory. In a data processing device that has an instruction buffer for storing a specific branch instruction, a circuit detects a specific branch instruction and detects that all consecutive instructions from the branch destination of the branch instruction to that branch instruction can be stored in the instruction buffer. If a circuit detects a specific branch instruction and detects that the instructions from the branch destination of the branch instruction to the branch instruction itself can enter the instruction buffer, the circuit from the branch destination of the branch instruction to the branch instruction itself Once an instruction has been read, the instruction string is saved in the instruction buffer, and as long as the branch condition for that branch is met, a means is provided for directly retrieving the instruction from the instruction buffer without waiting for the instruction to be read from memory. A data processing device that uses Z%.