JPH04344531A - Instruction fetching control system - Google Patents

Abstract

PURPOSE:To improve the branching action performance in an electronic computer equipped with a processor and a cache to perform the instruction fetching by the burst transfer of a fixed word unit. CONSTITUTION:When a branching control circuit 16 decodes an instruction extracted by a multiplexer 15 and detects the branching, the circuit outputs the branching instruction to a pre-fetching control circuit 14. A branching destination address calculating circuit 17, when the branching instruction is outputted from the multiplexer 15, sets the branching destination address to a branching destination address register 11. The pre-fetching control circuit 14, when the branching instruction is added, sets the branching destination address to a pre- fetching address counter 12 and outputs a cycle starting signal CST to instruct the fetching start. Thus, an address latch circuit 21 holds the branching destination address from the pre-fetching address counter 12 and a transfer control circuit 23 transfers the instruction shown by the content of the address latch circuit 21 stored in a memory 24 to a processor 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction fetch control system in an electronic computer equipped with a processor and a cache.

0002

2. Description of the Related Art In order to increase speed in electronic computers equipped with a processor and a cache, the processor has conventionally prefetched instructions. By the way, prefetching of instructions is performed by transferring fixed word length data from the cache to the processor in bursts, but conventionally, when a burst transfer is started, the next burst transfer is started until the previous burst transfer is completed. I couldn't do it.

0003

[Problems to be Solved by the Invention] As mentioned above, conventionally, when burst transfer is started, until it is completed,
The next burst transfer could not be started, so
Even if the processor detects a branch, if it is in the middle of an instruction fetch burst transfer, it cannot perform the burst transfer to fetch the branch destination instruction until that burst transfer has finished. . Therefore,
In the conventional example, there was a problem in that the performance of branch operations, which greatly affects computer performance, deteriorated due to fetching of unnecessary instructions.

An object of the present invention is to improve the performance of branching operations.

[0005]

Means for Solving the Problems In order to achieve the above object, the present invention provides an electronic computer equipped with a processor that performs burst transfer in fixed word units to and from a cache to fetch instructions. , a prefetch address counter that outputs a fetch destination address to the cache, a prefetch buffer that holds instructions transferred from the cache in an empty space, and a branch that sequentially decodes the instructions held in the prefetch buffer. a branch control circuit that outputs a branch instruction by detecting and sets a branch destination address in the prefetch buffer; and a branch control circuit that outputs a branch instruction and sets a branch destination address in the prefetch buffer; By incrementing the prefetch address counter and outputting a fetch start instruction to the cache, and by outputting a branch instruction from the branch control circuit, all the prefetch buffers are emptied and the cache is sent to the cache. a prefetch control circuit that outputs a fetch start instruction, and the cache holds a memory in which instructions for the processor are stored and an address output from the prefetch address counter in response to the fetch start instruction. an address latch circuit; and a transfer control circuit for sequentially burst-transferring instructions stored in an address held by the address latch circuit of the memory to the processor from a first word in response to the fetch activation instruction. It is something that

[0006]

[Operation] The prefetch control circuit increments the prefetch address counter when the burst transfer in units of fixed words is completed and there is space for the fixed words in the prefetch buffer, and further instructs the cache to start fetching. Output.

The address latch circuit in the cache holds the output of the prefetch address counter in response to a fetch activation instruction, and the transfer control circuit holds the output of the prefetch address counter in response to a fetch activation instruction, and the transfer control circuit holds the output of the prefetch address counter in response to a fetch activation instruction, and the transfer control circuit holds the output of the prefetch address counter in response to a fetch activation instruction. The stored instructions are sequentially burst-transferred to the processor starting from the first word.

[0008] Instructions burst-transferred from the processor are sequentially stored in a prefetch buffer within the processor. During burst transfer, when the branch control circuit decodes the instructions stored in the prefetch buffer and detects a branch, the branch destination address is set in the prefetch address counter and a branch instruction is output to the prefetch control circuit. be done. The prefetch control circuit empties all prefetch buffers by adding a branch instruction, and then outputs a fetch activation instruction to the cache.

When the above-mentioned fetch activation instruction is applied while a burst transfer is being performed, the transfer control circuit in the cache interrupts the burst transfer currently being performed, and the address latch circuit of the memory in which instructions for the processor are stored is activated. The instructions stored at the address held by the CPU (branch destination address) are sequentially burst-transferred from the 1-word memory to the processor.

0010

Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which is composed of a processor 1 and a cache 2.

The processor 1 has a branch destination address register 11 that holds a branch destination address, a prefetch address counter 12 that holds a fetch address, and a prefetch address register 12 that holds data (instructions) transferred from a cache 2.
a set of prefetch buffers 13-1 and 13-2, and a prefetch control circuit 14 that controls the prefetch buffers 13-1 and 13-2 and outputs a cycle start signal CST that instructs the cache 2 to start fetching; A multiplexer 15 that selects one of the prefetch buffers 13-1 and 13-2, and a branch that outputs a branch instruction to the prefetch control circuit 14 by decoding the instruction output from the multiplexer 15 and detecting a branch. It includes a control circuit 16 and a branch destination address calculation circuit 17 that calculates a branch destination address. Note that the prefetch buffers 13-1 and 13-2 both have 4
It has a capacity that can hold data for words and a valid bit for each word (a bit indicating whether the word is valid or not).

The cache 2 controls the address latch circuit 21 that holds the address ADD output from the prefetch address counter 12, the word counter 22, and the word counter 22, and also outputs a data response signal RDY to the processor 1. Transfer control circuit 2
3, a memory 24 in which instructions for the processor 1 are stored, and a multiplexer 25 that selects one of the four words of data output from the memory 24, and the data DAT selected by the multiplexer 25. is transferred to processor 1.

Next, the operation of this embodiment will be explained. In this embodiment, it is assumed that one burst transfer is performed in units of four words.

First, a normal fetch operation that does not involve branches will be explained.

The prefetch control circuit 14 changes the contents of the prefetch address counter 12 to
1, a cycle start signal CST is output to the cache 2. In the initial state, both prefetch buffers 13-1 and 13-2 are empty, so the prefetch control circuit 14 outputs a cycle start signal CST to the cache 2. After incrementing the contents of the prefetch counter 12 by 1, a cycle start signal CST is output to the cache 2.

When the cycle start signal CST is output from the prefetch control circuit 14, the address latch circuit 21 in the cache 2 holds the fetch destination address ADD output from the prefetch address counter 12, and the transfer control circuit 23 holds the fetch destination address ADD output from the prefetch address counter 12. An initial value "0" is set in the word counter 22. By holding the fetch destination address in the address latch circuit 21, four words of data stored in parallel at that address are read from the memory 24 and added to the multiplexer 25. The multiplexer 25 transfers the first word of data indicated by the word counter 22 of the added four words of data to the processor 1. At the same time, the transfer control circuit 23 outputs the data response signal RDY.

When the data response signal RDY is applied, the prefetch control circuit 14 sends the first word to one of the two sets of prefetch buffers 13-1 and 13-2 (referred to as prefetch buffer 13-1). Instructs the area to hold data from cache 2. As a result, the prefetch buffer 13-1 holds the data from the cache 2 in the first word area, and sets the valid bit corresponding to the word to be valid.

Further, when the transfer control circuit 23 outputs the data response signal RDY, the word counter 22 is incremented by one. As a result, the multiplexer 25 selects the second word of data and transfers it to the processor 1. Thereafter, data up to the fourth word is burst transferred to the processor 1 in the same manner.

When the fourth word transfer is completed, the prefetch control circuit 14 receives the fourth data response signal RD.
When Y is added, one prefetch buffer 13-
2 is empty, and there is space for four words or more, so a cycle start signal CST is output and a transfer request for the next four words of instructions is made.

Next, a fetch operation including a branch will be explained.

The branch control circuit 16 decodes the instruction extracted by the multiplexer 15, and when a branch is detected, outputs a branch instruction to the prefetch control circuit 14. Further, when a branch instruction is output from the multiplexer 15, the branch destination address calculation circuit 17 calculates a branch destination address and sets it in the branch destination address register 11.

When a branch instruction is applied, the prefetch control circuit 14 unconditionally operates the prefetch buffer 13-- if the burst transfer is not in progress, and if the burst transfer is in progress, the prefetch control circuit 14 controls the prefetch buffer 13- 1 and 13-2 to empty the prefetch buffers 13-1 and 13-2, and further transfer the branch destination address set in the branch destination address register 11 to the prefetch address counter 1.
2 and outputs a cycle start signal CST to cache 2.

Address latch circuit 21 in cache 2
When the cycle start signal CST is output, the branch destination address outputted from the prefetch address counter 12 is held, and the transfer control circuit 23 sets the contents of the word counter 22 to the initial value "0". As a result, a fetch operation similar to that described above is performed, and the instructions indicated by the address held in the address latch circuit 21 are sequentially burst-transferred to the processor 1 from the first word.

[0025]

As explained above, when the branch control circuit decodes an instruction and detects a branch, the present invention interrupts the burst transfer even in the middle of the burst transfer for lookahead, and This starts a burst transfer for new prefetching based on an address, and unnecessary fetches are not performed, which has the effect of improving branch operation performance compared to the conventional example.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention.

[Explanation of symbols]

1... Processor 2... Cache 11... Branch destination address register 12... Prefetch address counter 13-1, 13-2... Prefetch buffer 14... Prefetch control circuit 15, 25... Multiplexer 16... Branch control circuit 17... Branch destination address calculation circuit 21 ...Address latch circuit 22...Word counter 23...Transfer control circuit 24...Memory

Claims (3)

[Claims] 1. In an electronic computer equipped with a processor that performs burst transfer in fixed word units to and from a cache to fetch instructions, the processor performs a prefetch process that outputs a fetch destination address to the cache. an address counter; a prefetch buffer that holds instructions transferred from the cache in an empty space; a branch instruction that is output by sequentially decoding the instructions held in the prefetch buffer to detect a branch; a branch control circuit that sets a branch destination address in the cache; and a branch control circuit that increments the prefetch address counter when the fixed word burst transfer is completed and there is space for the fixed word in the prefetch buffer. a prefetch control circuit that outputs a fetch start instruction to the cache, empties all the prefetch buffers by outputting the branch instruction from the branch control circuit, and outputs a fetch start instruction to the cache; The cache includes a memory in which instructions for the processor are stored, an address latch circuit that holds the address output from the prefetch address counter in response to the fetch activation instruction, and an address latch circuit that holds the address output from the prefetch address counter in response to the fetch activation instruction. An instruction fetch control system comprising: a transfer control circuit that burst-transfers instructions stored at an address held by the address latch circuit of a memory to the processor sequentially from a first word. 2. The prefetch buffer has a valid bit for each word, and the valid bit indicates whether each word is empty or not.
The instruction fetch control method described. 3. The transfer control circuit has a word counter, sets an initial value to the word counter in response to the fetch activation instruction, and sets the word counter to an initial value, and sets the initial value to the word counter, and sets the initial value to the word counter in response to the fetch start instruction. 3. The instruction fetch control method according to claim 2, wherein the data indicated by the word counter among the data being stored is transferred to the processor, and the count value is incremented upon completion of the transfer.