JPS6161419B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention saves necessary data read from memory during instruction execution in an information processing device in a memory provided separately from the instruction processing memory, and prevents data from being processed in units of instructions in the event of an error. This invention relates to a data save control method for restoring saved data to the original instruction processing memory to return to the state before the instruction was executed when retrying the instruction.

Instructions and data read from the memory for instruction processing enter registers, are decoded, and are executed and processed instruction by instruction. However, if an error occurs during data processing, the system returns to the state before the instruction was executed and tries again. There is a need. Depending on the instruction, for example, the memory contents at the address may be changed by +1, -1, 2 ⁿ times, etc., so the data may have already been updated and changed at this time. Therefore, it is necessary to save the data read from the memory and restore it to the memory. Now, in this case, it is sufficient if only the data actually used in the instruction is saved, but when memory is shared by multiple processing units, it is not desirable to save and restore more data than necessary to avoid interference. . If the beginning of the used data does not match the boundary of the memory read width (for example, a 4-byte or 8-byte boundary), you can extract only the necessary data, or conversely, it takes a few bytes to align the position when restoring. Requires alignment. In other words, data stored in memory is given an address in units of bytes, so that one byte is a unit of processing, but data is usually read out from memory in units of one word (for example, 4 bytes or 8 bytes) at a time, and instructions are not used. Not all bytes in a word are necessarily used, and the data to be restored does not necessarily match the beginning of the word, so complex control is required, such as so-called byte alignment, which discards unnecessary data and aligns the beginning. There are drawbacks.

The purpose of the present invention is to eliminate the above-mentioned complicated control and to greatly simplify the machine check handler (a program or microprogram that is activated when an error occurs to record and recover from the error) so that it can be retried in a short time. The purpose is to improve the operating rate of an information processing device by making preparations possible.

When reading one word containing necessary data, the present invention saves all the data of one word as is without byte alignment, and at the same time changes the memory address of the word, the access direction, (the two used in the instruction)
Save a byte mark indicating the data length or the required byte position (indicating whether the addresses of the above bytes are arranged in the increasing direction from the word break or in the opposite direction). Furthermore, a counter is provided to indicate whether data is saved or not and the number of words of saved data. The counter is cleared at the start of execution of an instruction, and is incremented by the number of words saved each time it is saved. Restoring saved data, addresses,
It is sufficient to perform the process as many times as indicated on the counter using the access direction, data length, etc.

A detailed explanation will be given below according to the drawings.

The drawing is a block diagram of a circuit showing one embodiment of the present invention, and only parts related to the present invention are shown and other parts are omitted. 1 is a memory, 2 is a memory address register, 3 is a length register, 4 is an access direction register, 5 is a counter, 6 is an address save memory, 7 is a data save memory, 8 is a processing unit, 9 and 10 are control circuits It is. Processing device 8
, the memory 1, the memory address 2, and the control circuit 9 are the main parts constituting the information processing apparatus, and the others and a part of the control circuit 9 are parts related to the present invention. Data that needs to be saved among the data read out from the memory 1 according to the address specified by the memory address register 2 is stored in the data save memory 7, while the memory address, access direction, data length, etc. are stored in the address save memory 6. The data is entered and saved, and the counter 5 is counted up. However, the counter 5 is cleared at the start of execution of the instruction, and is incremented every time the instruction is saved.
When an error occurs, restoration is performed, but the contents of the counter 5 are checked, and if it is 0, it is determined that restoration is not necessary, and if a certain amount is indicated, restoration is performed while counting down. That is, the output of the address save memory 6 is returned to the memory address register 2, length register 3, and access direction register 4 via the control circuit 10, so that the address, access direction, data length, etc. of the memory 1 are the same as when they were read. The control circuit 9 restores the data read out from the data save memory 7 to the memory 1 using a memory write circuit (not shown) during normal operation, and the counter 5 counts down. The same operation as above is repeated until the counter 5 reaches 0.

As explained above, according to the present invention, saving and restoring can be performed without being aware of the position of data within a word, the access direction, the difference between byte-by-byte access and continuous access of data, etc., and does not require complicated control. Since the counter alone can distinguish whether an instruction requires save data or the difference in the amount of save data for each instruction, there is no need to perform different controls for each instruction, which greatly simplifies the machine check handler and saves time. Now you can prepare to try again.

[Brief explanation of the drawing]

The drawing is a block diagram of a circuit showing one embodiment of the present invention. 1 is a memory, 2 is a memory address register, 3 is a length register, 4 is an access direction register, 5 is a counter, 6 is an address save memory, 7 is a data save memory, 8 is a processing unit, 9 and 10 are control circuits It is.

Claims (1)

[Claims] 1. A first storage unit storing data to be processed by an instruction.
and a second memory for storing save information independent of the first memory, and during execution of an instruction, necessary data read from the first memory to be processed by the instruction is stored in the second memory. The data is stored in a memory, and when an error occurs, the data stored in the second memory is used to reproduce the state before the instruction execution, and in an information processing device that retries the instruction, the data is transferred from the first memory to the second memory. Storing all of the plurality of processing units in one word of read data, and
A data save control method characterized in that information indicating a memory address related to accessing the data and a range of processing units used in the instruction processing within a word is also stored. 2. The second memory has a counter for indicating the position of the last stored data, and the counter is cleared at the start of instruction execution, and is incremented each time data is stored. A data save control method according to claim 1.