JPS54159133A - Buffer memory system - Google Patents

Buffer memory system

Info

Publication number
JPS54159133A
JPS54159133A JP6779078A JP6779078A JPS54159133A JP S54159133 A JPS54159133 A JP S54159133A JP 6779078 A JP6779078 A JP 6779078A JP 6779078 A JP6779078 A JP 6779078A JP S54159133 A JPS54159133 A JP S54159133A
Authority
JP
Japan
Prior art keywords
block
main memory
memory
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6779078A
Other languages
Japanese (ja)
Inventor
Seiichiro Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6779078A priority Critical patent/JPS54159133A/en
Publication of JPS54159133A publication Critical patent/JPS54159133A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the probability of required block in existing in BM, by transferring the block from the main memory only when the accessing is made by instruction readout, of no block desired to be accessed is present to the buffer memory BM.
CONSTITUTION: The tag bit of the address of the block stored in BM1 and the memory address accessed are compared at the block address coincidence detection circuit 2 to discriminate whether the block accessed is present at BM1 or not. When the addresses are in agreement with each other, the address coincidence detection signal 9 is turned on to control the memory control circuit 4. The circuit 4 controls with the output of the signal 9 for accessing to BM1 or to the main memory 3, and if the access block is not present in BM1, and if the instruction readout display signal 8 causes the intruction readout, the block is transferred from the main memory 3 to the block 1. If the signal 8 does not indicate the instruction readout, the circuit 4 accesses to the main memory. Thus, the probability of required blocks in existing in BM can be increased.
COPYRIGHT: (C)1979,JPO&Japio
JP6779078A 1978-06-07 1978-06-07 Buffer memory system Pending JPS54159133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6779078A JPS54159133A (en) 1978-06-07 1978-06-07 Buffer memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6779078A JPS54159133A (en) 1978-06-07 1978-06-07 Buffer memory system

Publications (1)

Publication Number Publication Date
JPS54159133A true JPS54159133A (en) 1979-12-15

Family

ID=13355091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6779078A Pending JPS54159133A (en) 1978-06-07 1978-06-07 Buffer memory system

Country Status (1)

Country Link
JP (1) JPS54159133A (en)

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