JPS5690359A - Information control unit - Google Patents

Information control unit

Info

Publication number
JPS5690359A
JPS5690359A JP16872179A JP16872179A JPS5690359A JP S5690359 A JPS5690359 A JP S5690359A JP 16872179 A JP16872179 A JP 16872179A JP 16872179 A JP16872179 A JP 16872179A JP S5690359 A JPS5690359 A JP S5690359A
Authority
JP
Japan
Prior art keywords
memory
circuit
address
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16872179A
Other languages
Japanese (ja)
Inventor
Rikuro Yoshimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16872179A priority Critical patent/JPS5690359A/en
Publication of JPS5690359A publication Critical patent/JPS5690359A/en
Pending legal-status Critical Current

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Landscapes

  • Storage Device Security (AREA)

Abstract

PURPOSE: To protect memory information of a memory device, by providing the function for confirming the correctness of the memory address to be accessed, in case of transferring the information to the memory device.
CONSTITUTION: The precedence is given to the transfer request 21 from each device, and the transfer type designation 22, by the priority circuit 10. The highest precedence transfer request 27 and its transfer type designation 26 become indexes of the memory part 12. The memory part 12 consists of an effective fit part 41, a relative address designation part 42 and an address part 43, which output an effective bit 32, a relative address designation 33 and an address 34, respectively. The comparator 13 compares the output addresses 31, 34 of the selecting circuit 11 and the memory part 12 in accordance with the instruction of the bit 32 and the address designation 33, and in case of coincidence of the compared results, a coincidence signal 36 is output. The output of the NAND circuit 14 which inputs the effective bit 32 becomes an approval signal 41 together with the signal 36, by the OR circuit 15. The transfer request 27 to which the precedence has been given by the circuit 10 requests a memory access 42 through the AND circuit 16 only when the signal 41 has shown the approval state.
COPYRIGHT: (C)1981,JPO&Japio
JP16872179A 1979-12-25 1979-12-25 Information control unit Pending JPS5690359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16872179A JPS5690359A (en) 1979-12-25 1979-12-25 Information control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16872179A JPS5690359A (en) 1979-12-25 1979-12-25 Information control unit

Publications (1)

Publication Number Publication Date
JPS5690359A true JPS5690359A (en) 1981-07-22

Family

ID=15873200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16872179A Pending JPS5690359A (en) 1979-12-25 1979-12-25 Information control unit

Country Status (1)

Country Link
JP (1) JPS5690359A (en)

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