JPS6435648A - Combined series system - Google Patents

Combined series system

Info

Publication number
JPS6435648A
JPS6435648A JP19155287A JP19155287A JPS6435648A JP S6435648 A JPS6435648 A JP S6435648A JP 19155287 A JP19155287 A JP 19155287A JP 19155287 A JP19155287 A JP 19155287A JP S6435648 A JPS6435648 A JP S6435648A
Authority
JP
Japan
Prior art keywords
address space
mmax1
memory
mmax2
memory address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19155287A
Other languages
Japanese (ja)
Inventor
Kunihiko Sakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19155287A priority Critical patent/JPS6435648A/en
Publication of JPS6435648A publication Critical patent/JPS6435648A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To switch and use a memory address space within a range indicated by a first and a second registering means as a main storage address space and a shared memory address space as well by instructing the said memory address space by a program status word. CONSTITUTION:A main storage device 24 and a shared memory device 23 are packaged for the memory address space, which can be accessed from data processing devices 21, 22. Namely, the device 24 is of the same size as the memory address space using an MMAX1 as the maximum address, and has a memory area to which all the address space can be assigned. The device 23 is of the size indicated by MMAX1-MMAX2, and has the memory area indicated by MMAX2+1-MMAX1. For example of the device 21, the address space within the range of MMAX2+1-MMAX1 is made to be assigned to one of either the device 24 or the device 23, according to the logical state of the expansion/contraction instruction bit 34 of the PSW33.
JP19155287A 1987-07-31 1987-07-31 Combined series system Pending JPS6435648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19155287A JPS6435648A (en) 1987-07-31 1987-07-31 Combined series system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19155287A JPS6435648A (en) 1987-07-31 1987-07-31 Combined series system

Publications (1)

Publication Number Publication Date
JPS6435648A true JPS6435648A (en) 1989-02-06

Family

ID=16276574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19155287A Pending JPS6435648A (en) 1987-07-31 1987-07-31 Combined series system

Country Status (1)

Country Link
JP (1) JPS6435648A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7088043B2 (en) 2004-04-09 2006-08-08 Samsung Electronics Co., Ltd. Plasma display panel enhancing a bright room contrast

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7088043B2 (en) 2004-04-09 2006-08-08 Samsung Electronics Co., Ltd. Plasma display panel enhancing a bright room contrast

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