JPS54128638A - Control system for cash memory - Google Patents

Control system for cash memory

Info

Publication number
JPS54128638A
JPS54128638A JP3609478A JP3609478A JPS54128638A JP S54128638 A JPS54128638 A JP S54128638A JP 3609478 A JP3609478 A JP 3609478A JP 3609478 A JP3609478 A JP 3609478A JP S54128638 A JPS54128638 A JP S54128638A
Authority
JP
Japan
Prior art keywords
bits
memory
cash
cash memory
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3609478A
Other languages
Japanese (ja)
Inventor
Takashi Rokutanda
Yoshiyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3609478A priority Critical patent/JPS54128638A/en
Publication of JPS54128638A publication Critical patent/JPS54128638A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To perform good efficient control, by optimizing the size of the block transferred to the cash memory from the main memory through the change of size, and increasing the efficiency of execution of the cash memory.
CONSTITUTION: In the data processor having the cash memory, the address register 41 entrying the address is provided to use the area having the main memory by CPU as the hardware fixed area, and the bits 12 to 21 are taken as the field to designate the bank, the bits 22 to 27 are taken as the priority designation field, and the bits 28 to 31 are taken as the block designation field. Further, the size of the transfer block of the cash memory is changed by adding the bits 501 to 504 to the flag bits 491 to 494 with the bit 28 of the register 41. Further, when the access of main memory is incoming from CPU, the registration of the directory 42 is detected with the output of the comparator 43, and when this output is present, CPU accesses the main memory, not the cash memory.
COPYRIGHT: (C)1979,JPO&Japio
JP3609478A 1978-03-30 1978-03-30 Control system for cash memory Pending JPS54128638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3609478A JPS54128638A (en) 1978-03-30 1978-03-30 Control system for cash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3609478A JPS54128638A (en) 1978-03-30 1978-03-30 Control system for cash memory

Publications (1)

Publication Number Publication Date
JPS54128638A true JPS54128638A (en) 1979-10-05

Family

ID=12460162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3609478A Pending JPS54128638A (en) 1978-03-30 1978-03-30 Control system for cash memory

Country Status (1)

Country Link
JP (1) JPS54128638A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01184763A (en) * 1988-01-20 1989-07-24 Hitachi Ltd Data storage system in file system
JP2001175534A (en) * 1999-12-17 2001-06-29 Sanyo Electric Co Ltd Memory control circuit
JP2007520813A (en) * 2004-01-15 2007-07-26 インテル コーポレイション Multiprocessor computing system using word of information of compressed cache line and processor usable in the system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929536A (en) * 1972-07-14 1974-03-16
JPS49113537A (en) * 1973-02-26 1974-10-30
JPS5014239A (en) * 1973-06-06 1975-02-14
JPS5017741A (en) * 1973-06-18 1975-02-25

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929536A (en) * 1972-07-14 1974-03-16
JPS49113537A (en) * 1973-02-26 1974-10-30
JPS5014239A (en) * 1973-06-06 1975-02-14
JPS5017741A (en) * 1973-06-18 1975-02-25

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01184763A (en) * 1988-01-20 1989-07-24 Hitachi Ltd Data storage system in file system
JP2001175534A (en) * 1999-12-17 2001-06-29 Sanyo Electric Co Ltd Memory control circuit
JP2007520813A (en) * 2004-01-15 2007-07-26 インテル コーポレイション Multiprocessor computing system using word of information of compressed cache line and processor usable in the system

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