JPS5587363A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS5587363A
JPS5587363A JP16039578A JP16039578A JPS5587363A JP S5587363 A JPS5587363 A JP S5587363A JP 16039578 A JP16039578 A JP 16039578A JP 16039578 A JP16039578 A JP 16039578A JP S5587363 A JPS5587363 A JP S5587363A
Authority
JP
Japan
Prior art keywords
memory
access
data
address
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16039578A
Other languages
Japanese (ja)
Inventor
Akira Hattori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16039578A priority Critical patent/JPS5587363A/en
Publication of JPS5587363A publication Critical patent/JPS5587363A/en
Pending legal-status Critical Current

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Landscapes

  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To secure a simple constitution for the control unit with no address register required by giving the control to the buffer memory to which the data of the main memory and part of the address are written via the flag memory possessing the fixed set and others.
CONSTITUTION: If the address exists in tag memory 2 at the access time due to the address given from buffer address register 1, the data of data memory 3 is delivered through selector 7 which is controlled via comparators 6 and 6'. In this case, if the index access of memory 2, the storage of the data and the preceding access do not exist, the output of comparators 6 and 6' feature a low level. At the same time, the output also features a low level for flag memory 13 which has no preceding access and possesses the set corresponding to the set of main memory 16, and the output of AND circuit 14 with NOT features a high level. Thus AND gate 13 opens with the access given to memory 16. In case the preceding access exists, gate 15 does not open. Thus the double storage can be avoided for the data same as the preceding access into memory 3.
COPYRIGHT: (C)1980,JPO&Japio
JP16039578A 1978-12-25 1978-12-25 Buffer memory control system Pending JPS5587363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16039578A JPS5587363A (en) 1978-12-25 1978-12-25 Buffer memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16039578A JPS5587363A (en) 1978-12-25 1978-12-25 Buffer memory control system

Publications (1)

Publication Number Publication Date
JPS5587363A true JPS5587363A (en) 1980-07-02

Family

ID=15714018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16039578A Pending JPS5587363A (en) 1978-12-25 1978-12-25 Buffer memory control system

Country Status (1)

Country Link
JP (1) JPS5587363A (en)

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