JPS54142021A - Data process system - Google Patents

Data process system

Info

Publication number
JPS54142021A
JPS54142021A JP5055878A JP5055878A JPS54142021A JP S54142021 A JPS54142021 A JP S54142021A JP 5055878 A JP5055878 A JP 5055878A JP 5055878 A JP5055878 A JP 5055878A JP S54142021 A JPS54142021 A JP S54142021A
Authority
JP
Japan
Prior art keywords
memory
information
address
registers
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5055878A
Other languages
Japanese (ja)
Inventor
Takeshi Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5055878A priority Critical patent/JPS54142021A/en
Publication of JPS54142021A publication Critical patent/JPS54142021A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enhance the probability for existence of the desired information on the buffer memory by forming the buffer memory with n-pairs of block units and then providing the memory address register to the buffer memory in 1:1 ratio correspondence.
CONSTITUTION: The information on main memory 1 is stored into buffer memory 2 in the block unit of 2-0, 2-1W2-n and also corresponded in 1:1 to address registers 3-0, 3-1W3-n. At the same time, registers 3-0, 3-1W3-n are corresponded to the memory contents on memory 1 based on decision at the CPU side. In other words, the address information is set to register 3-0 to give an access to the order information on memory 1, and the address information is set to other registers 3-1W3-n to give an access to the operation information of memory 1 respectively.
COPYRIGHT: (C)1979,JPO&Japio
JP5055878A 1978-04-27 1978-04-27 Data process system Pending JPS54142021A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5055878A JPS54142021A (en) 1978-04-27 1978-04-27 Data process system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5055878A JPS54142021A (en) 1978-04-27 1978-04-27 Data process system

Publications (1)

Publication Number Publication Date
JPS54142021A true JPS54142021A (en) 1979-11-05

Family

ID=12862330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5055878A Pending JPS54142021A (en) 1978-04-27 1978-04-27 Data process system

Country Status (1)

Country Link
JP (1) JPS54142021A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61271572A (en) * 1985-05-28 1986-12-01 Toshiba Corp Cache memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61271572A (en) * 1985-05-28 1986-12-01 Toshiba Corp Cache memory
JPH056705B2 (en) * 1985-05-28 1993-01-27 Tokyo Shibaura Electric Co

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