JPS5774891A - Logical circuit - Google Patents

Logical circuit

Info

Publication number
JPS5774891A
JPS5774891A JP55149775A JP14977580A JPS5774891A JP S5774891 A JPS5774891 A JP S5774891A JP 55149775 A JP55149775 A JP 55149775A JP 14977580 A JP14977580 A JP 14977580A JP S5774891 A JPS5774891 A JP S5774891A
Authority
JP
Japan
Prior art keywords
word address
test
memory
readout
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55149775A
Other languages
Japanese (ja)
Inventor
Hideo Shibano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55149775A priority Critical patent/JPS5774891A/en
Publication of JPS5774891A publication Critical patent/JPS5774891A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Abstract

PURPOSE:To perform the forming of test data and the test quickly and easily, by taking only the word address specific to the memory section as the objective of write-in and readout, at the via a control gate. CONSTITUTION:In testing a memory 3 having a plurality of storage locations indicated with a word address, a control signal 10 is a low level and the output of each AND gate of a control circuit 11 is all zero. Thus, even if various word addresses 6 are applied from the 1st logical section 2, a word address 6' accessing the memory 3 is taken as a specific word address in which each bit is all zero at test. As a result, the forming of test data and the test by write-in and readout having a plurality of storage locations indicated with the word address of a logical circuit can be made quickly and easily.
JP55149775A 1980-10-24 1980-10-24 Logical circuit Pending JPS5774891A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55149775A JPS5774891A (en) 1980-10-24 1980-10-24 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55149775A JPS5774891A (en) 1980-10-24 1980-10-24 Logical circuit

Publications (1)

Publication Number Publication Date
JPS5774891A true JPS5774891A (en) 1982-05-11

Family

ID=15482450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55149775A Pending JPS5774891A (en) 1980-10-24 1980-10-24 Logical circuit

Country Status (1)

Country Link
JP (1) JPS5774891A (en)

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