JPS5672766A - Control system of memroy unit - Google Patents

Control system of memroy unit

Info

Publication number
JPS5672766A
JPS5672766A JP14973679A JP14973679A JPS5672766A JP S5672766 A JPS5672766 A JP S5672766A JP 14973679 A JP14973679 A JP 14973679A JP 14973679 A JP14973679 A JP 14973679A JP S5672766 A JPS5672766 A JP S5672766A
Authority
JP
Japan
Prior art keywords
addresses
memory
memory units
arithmetic
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14973679A
Other languages
Japanese (ja)
Inventor
Tatsuo Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14973679A priority Critical patent/JPS5672766A/en
Publication of JPS5672766A publication Critical patent/JPS5672766A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To enable high-speed data processing by shortening memory cycles easily without using a high-speed memory element when repeatedly returning the arithmetic result of data read out of a memory unit. CONSTITUTION:Arithmetic between the output of multiplexer 24 and an operand is performed by operator 25, data to be written in memory units 211 and 212 are held in write registers 261 and 262, and addresses for memory units 211 and 212 are set in address counter 22 in common. Then, counter 22 is made to count up one by one successively and respective arithmetic results of contents of addresses A, A+1, A+2,... of memory units 211 and 212 are written in not the same addresses in memory units 211 and 212 but addresses preceding by one. When every address is assigned once, counter 22 is made to count down under the control of the arithmetic unit and this operation is repeated, so that the data can be processed at a high speed.
JP14973679A 1979-11-19 1979-11-19 Control system of memroy unit Pending JPS5672766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14973679A JPS5672766A (en) 1979-11-19 1979-11-19 Control system of memroy unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14973679A JPS5672766A (en) 1979-11-19 1979-11-19 Control system of memroy unit

Publications (1)

Publication Number Publication Date
JPS5672766A true JPS5672766A (en) 1981-06-17

Family

ID=15481679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14973679A Pending JPS5672766A (en) 1979-11-19 1979-11-19 Control system of memroy unit

Country Status (1)

Country Link
JP (1) JPS5672766A (en)

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