GB1218656A - Improvements in or relating to computer system - Google Patents
Improvements in or relating to computer systemInfo
- Publication number
- GB1218656A GB1218656A GB1473168A GB1473168A GB1218656A GB 1218656 A GB1218656 A GB 1218656A GB 1473168 A GB1473168 A GB 1473168A GB 1473168 A GB1473168 A GB 1473168A GB 1218656 A GB1218656 A GB 1218656A
- Authority
- GB
- United Kingdom
- Prior art keywords
- registers
- word
- main memory
- address
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
1,218,656. Computers. INTERNATIONAL COMPUTERS Ltd. 12 March, 1969 [27 March, 1968], No. 14731/68. Heading G4A. A data processing system comprises a main memory 10, a subsidiary memory 20 having two data word registers 21, 22 with respective address registers 23, 24 two operand address registers 25 which supply two addresses from an instruction to the address registers 23, 24 but only to one of them if the addresses are identical, means to read a data word from main to subsidiary memory using address registers 23, 24 if the word address was not already in either of registers 23, 24, means 35 to manipulate and modify separate bytes of data words in word registers 21, 22 and means to return modified data words to the main memory. One or two operand addresses from registers 25 are placed in turn into one or two of registers 23, 24, but in each case only if neither of the registers 23, 24 already contains the (an equal) address (26, 27 are match flip-flops). The register 23 or 24 is then used to address main memory 10 to access the corresponding data word via a buffer register 13 into the respective word register 21 or 22. Bytes from registers 21, 22 are manipulated at 35 and the results returned to register 21 or 22, with a respective flip-flop 31 being set corresponding to each byte position of register 21 or 22 thus modified. The modified word is then returned to main memory 10 by reading the main memory word out to buffer 13, replacing only the modified bytes from register 21 or 22, under control of flip-flops 31, then rewriting the main memory word into main memory 10. As implied, address registers 23, 24 normally contain the main memory addresses of the data words in word registers 21, 22. If these addresses are changed from registers 25 as described above, the words in registers 21, 22 are restored to main memory first. The apparatus can be used for operating on individual bytes, or on multi-byte fields consisting of successive bytes in one or more words. For example, a multibyte field can be shifted from a position in one set of words to a position in another set. If the two sets are the same, the effect is to replicate the first byte of the source field in each byte position of the sink field.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1473168A GB1218656A (en) | 1968-03-27 | 1968-03-27 | Improvements in or relating to computer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1473168A GB1218656A (en) | 1968-03-27 | 1968-03-27 | Improvements in or relating to computer system |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1218656A true GB1218656A (en) | 1971-01-06 |
Family
ID=10046489
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1473168A Expired GB1218656A (en) | 1968-03-27 | 1968-03-27 | Improvements in or relating to computer system |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1218656A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2316658A1 (en) * | 1975-07-01 | 1977-01-28 | Siemens Ag | Byte field machine instruction organisation - has microprogramme loops held in store with byte field organisation for microprogrammed processors(BE030177) |
DE3043100A1 (en) * | 1979-11-15 | 1981-05-27 | Nippon Electric Co., Ltd., Tokyo | DATA PROCESSOR WITH DATA CORRECTION FUNCTION |
EP0099620A2 (en) * | 1982-04-21 | 1984-02-01 | Digital Equipment Corporation | Memory controller with data rotation arrangement |
GB2146146A (en) * | 1980-05-30 | 1985-04-11 | Fairchild Camera Instr Co | Microprocessor |
WO1988002514A1 (en) * | 1986-10-03 | 1988-04-07 | Telefonaktiebolaget L M Ericsson | Method and device to execute two instruction sequences in an order determined in advance |
WO1988002513A1 (en) * | 1986-10-03 | 1988-04-07 | Telefonaktiebolaget L M Ericsson | Method and device to execute two instruction sequences in an order determined in advance |
-
1968
- 1968-03-27 GB GB1473168A patent/GB1218656A/en not_active Expired
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2316658A1 (en) * | 1975-07-01 | 1977-01-28 | Siemens Ag | Byte field machine instruction organisation - has microprogramme loops held in store with byte field organisation for microprogrammed processors(BE030177) |
DE3043100A1 (en) * | 1979-11-15 | 1981-05-27 | Nippon Electric Co., Ltd., Tokyo | DATA PROCESSOR WITH DATA CORRECTION FUNCTION |
GB2146146A (en) * | 1980-05-30 | 1985-04-11 | Fairchild Camera Instr Co | Microprocessor |
EP0099620A2 (en) * | 1982-04-21 | 1984-02-01 | Digital Equipment Corporation | Memory controller with data rotation arrangement |
EP0099620A3 (en) * | 1982-04-21 | 1986-01-22 | Digital Equipment Corporation | Memory controller with data rotation arrangement |
WO1988002514A1 (en) * | 1986-10-03 | 1988-04-07 | Telefonaktiebolaget L M Ericsson | Method and device to execute two instruction sequences in an order determined in advance |
WO1988002513A1 (en) * | 1986-10-03 | 1988-04-07 | Telefonaktiebolaget L M Ericsson | Method and device to execute two instruction sequences in an order determined in advance |
AU596234B2 (en) * | 1986-10-03 | 1990-04-26 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and device to execute two instruction sequences in an order determined in advance |
US4956770A (en) * | 1986-10-03 | 1990-09-11 | Telefonaktiebolaget L M Ericsson | Method and device to execute two instruction sequences in an order determined in advance |
US4985826A (en) * | 1986-10-03 | 1991-01-15 | Telefonaktiebolaget L. M. Ericsson | Method and device to execute two instruction sequences in an order determined in advance |
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