GB1041723A - A program-controlled computer co-acting with a store - Google Patents

Abstract

1,041,723. Digital computers. TELEFUNKEN PATENTVERWERTUNGSGESELLSCHAFT. June 7, 1963 [June 13, 1962], No. 22813/63. Heading G4A. In a serial digital computer employing variable length data words, addresses in the instruction words are also of variable length, and are augmented to provide a full length address for addressing the computer store. The computer described, which is a serial decimal machine in which decimal digits are represented by four binary digits in parallel and other characters by six bits plus a checking bit, comprises a magnetic core store 1; an arithmetic unit comprising a logical network 7 for combining the contents of registers 3, 4, 5, 6 and placing the result in registers 3 and 5; and a control section comprising a register 10 for the address of the next instruction, and current operand address registers 11, 12. In operation, for the addition of two multi-digit numbers, the addresses of the two operands are entered in registers 11, 12. The address in register 11 is effective via a store address register 2 to read out the first digit of the first operand to the register 3, the addresses in the registers 11, 12 are then interchanged, the address formerly in the register 12 being reduced by unity in an arithmetic network 9. The first digit of the second operand is then read out from the store 1 to the register 3 and combined in the logical network 7 with the first digit of the first operand which is now in the register 4 to produce a sum digit, entered in the register 3 for subsequent entry into the store 1, a carry digit being temporarily stored in the register 5. Subsequent decimal orders are dealt with similarly, the contents of registers 11, 12 being interchanged at each step with reduction by unity of the address formerly in the register 12. The computer has provision (not described) for modifying instruction words. Abbreviated addressing procedure.-Two constructions of the address register 11 are described. In the first construction, Fig. 2 (not shown), the register 11 comprises a 5-stage decimal shift register, each stage storing one decimal digit as four binary digits in parallel. When the control section requires transfer of an address to the register 11, the register is first cleared so that each stage stores decimal " 0 " by means of five clock pulses on leads L, T. The first address digit is applied from the store 1 via the register 4, Figs. 1 and 2, to the first stage 17 of the register 11. Subsequent digits are similarly received, the digits already in the register being shifted to subsequent stages, this process continuing until a character which is not a decimal digit is received by the register 4 and detected by gates 19, 20. If fewer than five digits have been received, the leading places are regarded as "0" to constitute a full address. The second form of the register 11, Fig. 4 (not shown), is generally similar but each stage such as 17 of the register is provided with an additional bi-stable element 23-28, a " 1 " being entered in the first element 25 in synchronism with each address digit, only those shift register stages being shifted in which the associated element 25-28 stores a " 1." The register 11 is not cleared of its former contents so that if less than five new address digits are entered, they form a full effective address in combination with the unchanged digits already in the register. A sub -routine requiring addresses only in a particular block of the store 1 can thus be stored with only a single initial full address, subsequent addresses in the subroutine being abbreviated.