GB1234431A - - Google Patents

Abstract

1,234,431. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 12 Sept., 1968 [27 Sept., 1967], No. 43385/68. Heading G4A. A data processing system comprises a main store, an auxiliary store capable of performing a plurality of read/write cycles during each read/write cycle of the main store, a first and a second address path for accessing the auxiliary store, and addressing means for utilizing the first address path to read out a main store address stored in the auxiliary store in order to access a location in the main store and for subsequently utilizing the first address path to access a location in the auxiliary store such that data can be transferred between the two locations. The main store holds data, instruction and control words. The auxiliary (" active ") store includes working space, and locations for an instruction counter and operand main store addresses. The word portion of an operand address read from auxiliary store is used to read an operand word from main to auxiliary store. An arithmetic logic unit receives operands from the auxiliary store serially by byte, a marker register holding the byte portions of the operand addresses (and having adders to increment/decrement them) selecting the bytes. The marker register also has a 4-bit mask (one bit per byte of a word) to control which bytes of a main store operand word are finally overwritten by result bytes, and being updated by the adders. Control words from main store are entered into a control register and recoded to control the system. Data words from main store can be gated to a main data bus also fed by the auxiliary store. Address decode means in the first address path of the auxiliary store can be fed with control words from main store (without passing through the control register) while address decode means in the second address path can be fed from the control register. Both decode means can also be fed from section and word select registers fed by the main data bus. The two address paths are used during different portions of a cycle. The word portion of the memory address register through which the main store is addressed has a sub-portion to select a memory module and a sub-portion to select a word within the module. Input to the first sub-portion can be inhibited while the second sub-portion is changed upon the selection of successive control words. Control words may be provided in main store for the control of input/output devices, and modification of control words under control of other control words is possible.