GB1146587A - Digital data processing systems - Google Patents

Abstract

1,146,587. Digital computers; data transfer. INTERNATIONAL COMPUTERS Ltd. 29 March, 1966 [31 March, 1965], No. 13710/65. Heading G4A. In a data processing system comprising a main store 100, one or more peripheral units 103 and a data processor 101, for example, consisting of an arithmetic unit 120 and a microprogram me unit 121, character-by-character transfer of data words between peripheral units 103 and a subsidiary or buffer store 110 is controlled by a control unit 113 independently of the main programme, interruption thereof only taking place when it is required to transfer a complete word between the subsidiary store 110 and the main store 100 under control of the processor 101. A priority unit 112 is provided for connecting the peripheral units 103 through a channel selector 108 to a data highway 109 according to a predetermined order of priority. Connection is provided by the priority unit 112 and the channel selector 108 to all peripheral units within the cycle time for reading successive characters from the fastest peripheral unit. The units 103A, 103B, 103C may be magnetic tape units and unit 103S a paper tape punch. Each data word may comprise four characters. The store 110 comprises a number of register sets 115, a respective set being provided for each of the fast peripheral units 103A-103C and a common set 115S for all the slow units such as 103S. On reading a data transfer instruction from the main store 100 and after checking that the relevant peripheral unit is available, the processor 101 transfers control information (number of characters and destination of data) to the registers 116, 117 of the set 115 corresponding to the required peripheral unit, transfers two words of data (in the case of transfers from the main store to the peripheral unit) from the main store 100 to the relevant word registers 118, 119 and then continue with the next main programme instruction. Transfer of data between registers 118, 119 and the peripheral units character-by-character and progressive updating of the control information in registers 116, 117 takes place under the control of the unit 113. After transfer of a complete word (as detected by a counter in unit 113), control unit 113 emits a signal which stimulates the processor 101 to interrupt the instruction then being performed, effect transfer in parallel of a single word between the subsidiary store 110 and main store 100, modify the control information in registers 116 and 117 (in the case of transfers to the main store) and return to the interrupted programme instruction. Whilst transfer is taking place between one of the registers 118 or 119 and the main store 100, transfer may continue to take place between the other register and the corresponding peripheral unit. When the required data transfer has been completed (as detected by the processor 101 or the control unit) the transfer operation is terminated by updating the control information in registers 116, 117 storing this in special locations of the main store 100 and returning control to the interrupted main programme instruction. In the case of transfers to and from the slower peripheral units such as 103S, the control information and partially assembled or transferred words in the register set 115S and relating to each respective peripheral unit are stored in the main store 100 between successive character transfers.