JPS5618787A - Time counting system - Google Patents

Time counting system

Info

Publication number
JPS5618787A
JPS5618787A JP9453379A JP9453379A JPS5618787A JP S5618787 A JPS5618787 A JP S5618787A JP 9453379 A JP9453379 A JP 9453379A JP 9453379 A JP9453379 A JP 9453379A JP S5618787 A JPS5618787 A JP S5618787A
Authority
JP
Japan
Prior art keywords
memory
address
value
adder
time counting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9453379A
Inventor
Masahiro Kuriyama
Hiroshi Takada
Yoshio Yamamuro
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9453379A priority Critical patent/JPS5618787A/en
Publication of JPS5618787A publication Critical patent/JPS5618787A/en
Application status is Pending legal-status Critical

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G3/00Producing timing pulses
    • G04G3/02Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/025Circuits for deriving low frequency timing pulses from pulses of higher frequency by storing time-date which are periodically investigated and modified accordingly, e.g. by using cyclic shift-registers

Abstract

PURPOSE:To accomplish the time counting without any counter provided on an information processing device by renewing the value from a word at the lower level of a time counting counter comprising a plurality of words provided on a memory. CONSTITUTION:A control circuit 7 sequentially assigns the address of a memory 2 by way of an address recorder 3 to store an initial reset data into the memory 2. The circuit 7 also sets the constant for a constant register 4. Then, it sends the address data to the address decoder 3 to control the memory 2, and the value is read out sequentially from the word at the lowest level in the counter area. The value is sent to an adder 5 to be added to the value of the constant register 4. Then, the control circuit 7 stores the addition data of the adder 5 into the original address of the memory 2. When generated in the adder 5, the carry is memorized to be added to the subsequent word.
JP9453379A 1979-07-25 1979-07-25 Time counting system Pending JPS5618787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9453379A JPS5618787A (en) 1979-07-25 1979-07-25 Time counting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9453379A JPS5618787A (en) 1979-07-25 1979-07-25 Time counting system

Publications (1)

Publication Number Publication Date
JPS5618787A true JPS5618787A (en) 1981-02-21

Family

ID=14112963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9453379A Pending JPS5618787A (en) 1979-07-25 1979-07-25 Time counting system

Country Status (1)

Country Link
JP (1) JPS5618787A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58193017U (en) * 1982-06-21 1983-12-22
JPS58193018U (en) * 1982-06-21 1983-12-22
JPS60170032U (en) * 1984-04-17 1985-11-11

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58193017U (en) * 1982-06-21 1983-12-22
JPS58193018U (en) * 1982-06-21 1983-12-22
JPS6237940Y2 (en) * 1982-06-21 1987-09-28
JPS6318755Y2 (en) * 1982-06-21 1988-05-26
JPS60170032U (en) * 1984-04-17 1985-11-11

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