JPS54141974A - Sequence control unit - Google Patents

Sequence control unit

Info

Publication number
JPS54141974A
JPS54141974A JP4879478A JP4879478A JPS54141974A JP S54141974 A JPS54141974 A JP S54141974A JP 4879478 A JP4879478 A JP 4879478A JP 4879478 A JP4879478 A JP 4879478A JP S54141974 A JPS54141974 A JP S54141974A
Authority
JP
Japan
Prior art keywords
control unit
program
content
memory
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4879478A
Other languages
Japanese (ja)
Other versions
JPS5856123B2 (en
Inventor
Yutaka Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP4879478A priority Critical patent/JPS5856123B2/en
Publication of JPS54141974A publication Critical patent/JPS54141974A/en
Publication of JPS5856123B2 publication Critical patent/JPS5856123B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a sequence control unit which can be easily corresponded to the relay sequence in programming by storing the content of arithmetic register for each program step in the linear number status memory.
CONSTITUTION: The data is read from the input-output control unit 1 according to the content of program read from the program memory 2, operated one bit in the arithmetic and control unit 3, and its result is transfered to the input-output control unit 1. The linear number status memory 10 contains addresses of the number equal to that of the program memory 2, and writes the content of arithmetic register 8 in the same address location as that of the program address for each completion of program step. The content of memory 10 can be read at any program step and can be handled like an ordinary input-output data.
COPYRIGHT: (C)1979,JPO&Japio
JP4879478A 1978-04-26 1978-04-26 Sequence control device Expired JPS5856123B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4879478A JPS5856123B2 (en) 1978-04-26 1978-04-26 Sequence control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4879478A JPS5856123B2 (en) 1978-04-26 1978-04-26 Sequence control device

Publications (2)

Publication Number Publication Date
JPS54141974A true JPS54141974A (en) 1979-11-05
JPS5856123B2 JPS5856123B2 (en) 1983-12-13

Family

ID=12813130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4879478A Expired JPS5856123B2 (en) 1978-04-26 1978-04-26 Sequence control device

Country Status (1)

Country Link
JP (1) JPS5856123B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59229607A (en) * 1983-06-10 1984-12-24 Yaskawa Electric Mfg Co Ltd Programmable controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59229607A (en) * 1983-06-10 1984-12-24 Yaskawa Electric Mfg Co Ltd Programmable controller

Also Published As

Publication number Publication date
JPS5856123B2 (en) 1983-12-13

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