JPS6426975A - Fft arithmetic unit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of an overflow at the time of FFT arithmetic operation by using a random access memory which outputs the result of comparison between FFT object data and overflow threshold value data and a register which holds the maximum value of the comparison result and then carrying out the scaling arithmetic to the FFT object data. CONSTITUTION:An address is written in a latch circuit 13 based on a chip selection signal CSA and conversion data is written in a RAM 10 based on a chip selection signal CSB. These writing steps are repeated by the frequency equal to the number of level steps of the FFT object data. Then a flip-flop 17 of a deciding result register 11 is cleared by a chip selection signal CSC and the scale value is changed to perform butterfly arithmetic for the FFT arithmetic while fetching successively the FFT object data into a data memory. Then the deciding result of this time is read by a chip selection signal CSD. Such steps are repeated by (n) steps with a 2<n>-point FFT. In other words, it is possible to cope with all FFT algorithms including those having fundamental numbers 2, 4, 8, etc. by only updating the conversion data written in a RAM in accordance with selection of FFT algorithms.