JPS615358A - Data processor - Google Patents

Abstract

PURPOSE:To make use of the function of a buffer memory by prefetching the next data at an idle time of an interface in a memory access mode of continuous addresses and then prefetching the subsequent memory accesses at an idle time of a memory control part in a single operand fetching mode. CONSTITUTION:The accesses are given to the continuous addresses in an instruction fetching mode or an operand fetching mode of a move instruction, etc. Therefore 64 bytes are added to the continuous addresses by an adder 11 even in case it is detected that the data to which an access is presently given exists in a buffer memory. Then those bytes are set to a prefetch port 16 under the control of a memory access mode detecting part 17. Thus a prefetching action is carried out. When it is detected in a memory access mode of a single operand that the corresponding data is not detected in the memory 6, a normal block fetching request is sent to a main memory 15. Then a prefetching action is carried out by the subsequent operand fetch address in parallel to a block fetching action until the corresponding address data is sent back.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a buffer memory and a prefetch function in a data processing apparatus having a block-by-block prefetch function for the buffer memory.

In a data processing device that is required to perform ultra-high-speed data processing and is equipped with a buffer memory, when the buffer memory is accessed and the data is not accessed, the data transfer (block fetch) operation from the main memory to the buffer memory is as follows: Although this is one of the causes of performance deterioration, it is unavoidable to some extent due to the limited capacity of the buffer memory.

However, ■When the instruction control unit and calculation unit are operating based on data in the buffer memory, the interface unit with the main memory is not used, and ■Once a block fetch operation is started, the data block is Until the data is transferred from the main memory, idle time occurs in the instruction control section and the calculation section.

There is a demand for an effective prefetch function that focuses on the fact that the performance of the data processing device can be improved by pre-fetching data deemed necessary into the buffer memory using the free timing shown in ■ above. It had been.

In addition, regarding memory access, when a certain instruction is fetched along with continuous operand data, the program repeatedly fetches instructions within a certain address range, including the above instruction. By prefetching the next program of the data block containing the above-mentioned instruction, processing performance can be expected to be improved.

Therefore, in the data processing device, fetch accesses from the instruction control unit to the memory control unit can be broadly classified into the following two types.

That is, +1) instruction fetch or operand fetch of consecutive addresses.

(2111-operand fetch of (discontinuous address).

Regarding (1), by prefetching the next data block, the hint rate for the buffer memory can be improved.

Regarding (2), the performance of the data processing device can be improved by reading operand data for subsequent memory access into the buffer memory.

From this point of view, the above (]), +2 for memory access
A prefetch function that takes advantage of the characteristics of 1 was required.

fb) Prior Art A conventional prefetch function in a data processing device having a buffer memory will be explained with reference to FIG.

First, in a normal fetch operation, the fetch address corresponding to the fetch request EAG from the instruction control unit (hereinafter referred to as IU) 1 is transferred to the execution address register (EAI?) 3 through the selector 2, and then stored in the buffer. Memory (BS) 6. and sofa memory (BS) 6
The tag section (TAG) 4 holding the address information of is accessed.

Tag section (TAG) 4. and coincidence detection circuit (1CH>
5, when it is detected that a data block corresponding to the fetch request (EAG) exists on the buffer memory (BS) 6, the data is read from the buffer memory (BS) 6 through the selector 7, and the data is read out from the buffer memory (BS) 6 through the selector 7. If the fetch request (EAG) is an instruction, it is sent to the instruction word register (tWR) 8 and then sent to IU 1; if the fetch request (EAG) is an operand fetch, it is sent to the operand word register (OWR) 9.
After being set to , it is sent to the calculation unit (EU) 10.

Tag section (TAG) 4. and coincidence detection circuit (MCI)
5, when it is detected that the data block does not exist on the buffer memory (BS) 6, the fetch address is transferred from the execution address register (EAR) 3 to the real address register (RAR) 13. Main memory address register (MSAR) 14 is sent to the main memory unit (hereinafter referred to as MCU) 1 along with the block fetch request.
Sent on 5th.

When the data block of the fetch address is transferred from the MCII 15, the data is registered in the buffer memory (BS) 6, and the address information is stored in the tag section (TA).
G) Controlled to register in 4.

At this time, the first data among the above data is registered in the buffer memory (BS) 6, and at the same time is stored in the instruction word register (IWR) 8 or operand word register (OWR) 9 by bypass operation. is,
IU 1. Or sent to the processing unit (EU) 1.0.

(The circuits for registration and bypass are not shown.) Next, regarding the prefetch operation, if continuous operand data is required, such as a move instruction, the move instruction is detected. Then, the operand address written to execution address register (IEAR) 3 is sent to adder (INC) 11, and the address obtained by adding address 64 for one block (at the time of 64 bytes/block) is sent to prefetch port (PF PORT). )
16, enter the execution address register (EAR) 3 through selector 2, and write the tag section (TAG) 4.
．． When the matching detection circuit (MC) 5 detects that the data block does not exist in the buffer memory (BS) 6, the execution address register (EA
R) ' Save the address of 3 to the real address register (RA
R) 13. Main memory address register (MSAR) 1
41m, along with a block fetch request, MCU 1
For example, while performing a move operation between the buffer memory (BS) 6 and the calculation unit (EU) 10,
In parallel with the move operation or the normal block feed 7
In parallel with the fetch operation, the block fetch for the above-mentioned prefetch has been performed.

(C) The problem that the invention aims to solve is that in the conventional method, there is only one prefetch function, which is performed only on continuous operand data as described above, Access is limited, there are few opportunities for prefetching,
There has been a problem in that the processing capacity of a data processing device having a buffer memory cannot be improved to near its maximum limit.

In view of the above conventional drawbacks, the present invention focuses on the characteristics of memory access, divides memory access from the instruction control unit of a data processing device into the two systems, and performs prefetch processing suitable for the characteristics of each memory access. The purpose is to provide a method for doing this.

(d) Means to solve the problem and this purpose is for memory accesses where address continuity is expected in the memory accesses, such as instruction fetches and consecutive operand fetches. Then, when the arithmetic unit, etc. is operating based on the data in the buffer memory, the data block whose address is obtained by adding the number of bytes of one block to the access address is
Focusing on the fact that the interface with the main storage device is free, or when a normal block fetch is already being performed, the next data block is prefetched in parallel with the block fetch operation. ■For a single operand fetch, use -mutant. t'a,,,a,,7□41,3 Yayo, "4M5" 9
The memory control unit, etc. takes note of the free time until ' is transferred to the buffer memory, and preempts the subsequent memory access.
This is achieved by providing means for detecting one case and means for switching between the two cases, and providing a method for performing a prefetch operation corresponding to each case.

In other words, according to the present invention, the two cases shown in ■ and ■ above are detected and the prefetch operation corresponding to each case is controlled to be performed, thereby maximizing the function of the buffer memory. This has the effect of improving the processing capacity of the data processing device by making it possible to use a limited running object.

if) Example Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.As is clear from a comparison with the conventional system shown in FIG.
T) 17 control signal S causes buffer memory (BS
) The feature is that the prefetch method for 6 is switched.

('a) Memory access from IU 1 is
Nochi.

Or prefetch operation in case of operand fetch of consecutive addresses.

Since instruction fetches and operand fetches such as move instructions continuously access consecutive addresses, the data at the currently accessed address is in the tag section (TAG) 4
．． Coincidence Detection Circuit (MCI) The selector 12 is controlled by the control signal S of the memory access type detection unit (MAFDET) 17, and the address added by the adder (ING) 11 is sent to the prefetch port (PF PORT) 16. , through selector 2, execution address register (EAI?) 3
and tag section (TAG) 4. When the coincidence detection circuit (MCI) 5 detects that a data block at the address exists in the buffer memory (BS) 6, the prefetch operation is terminated, and when the data block does not exist, the address is stored in the prefetch block. Along with the fetch request, the real address register (RAR) 13
．． It is sent to the MCU 15 through the main memory address register (MSAR) 14.

When the data block of the prefetch address is transferred from the MCU 15, the data is registered in the buffer memory (BS) 6, and the address information is stored in the tag section (T
AG) 4 and terminate the prefetch operation.

This operation is performed in parallel with the normal block fetch operation described in FIG. 2 when the normal block fetch operation is being performed.

(b) Prefetch when the access from IU 1 is a single (i.e., discontinuous address) operand fetch Since operand fetch such as a load instruction is completed in one access, the operand fetch address of the next instruction is Since the prefetch is unrelated to the fetch address, the prefetch as described in (a) above, in which the prefetch is performed using an address obtained by adding 64 bytes to the fetch address, is meaningless. Therefore, in the present invention, the following prefetch is performed.

In a certain single-operand memory access, a tag part (TAG) 4. The matching detection circuit (MCII) 6 detects that the data does not exist in the buffer memory (BS) 6, and according to the operation described in (a) above, the normal block fetch request force < MCU 11
If the data at that address is sent to MCU 1
1 to the buffer memory (BS) 6, a prefetch is controlled to be performed in parallel with the block fetch operation based on the address of the subsequent operand fetch.

Specifically, a normal block fetch request is l'1cU
When the next operand fetch address (EAG) coming from the IUI is set in the execution address register (EAR) 3, the address is sent under control from the memory access type detection unit (MAFDET) 17. The selector 12 is controlled by the signal S, and the address set in the execution address register (EAR) 3 is directly sent to the prefetch port (PP PORT) (i.e., without adding 64 in the adder (INC) 11).
) 16 and sends the address to the execution address register (EAR) 3 through the selector 2, and the tag section (TAG) 4. The data at the address is transferred to the buffer memory (BS) by the coincidence detection circuit (MCI) '5.
) 6, the prefetch operation is terminated, and when the data does not exist, the address of the execution address register (EAR) 3 is transferred to the real address register (RAR) 13. It is sent to the MCII 11 through the main storage address register (MSAR) 14 along with the block fetch request for prefetching.

When the data at the fetch address is transferred from the MCU 11, the data is transferred to the buffer memory (BS).
6, and the address information is registered in the tag section (TAG) 4, and this prefetch operation is completed.

In this way, in the present invention, the normal fetch operation explained in FIG.
It is characterized in that it operates by being dynamically switched by a control signal S from 17.

(a) Effects of the Invention As explained in detail above, the data processing device of the present invention has the advantage that, in memory accesses, address continuity is expected in the memory accesses, such as instruction fetches and consecutive operand fetches. When a memory access is performed, the data block at the address obtained by adding the number of bytes of one block (for example, 64) to the access address is stored in the main memory when the arithmetic unit is operating based on the data in the buffer memory. Focusing on the fact that the interface with the For the first operand fetch, we focused on the fact that when a normal block fetch operation starts, the memory control unit, etc. becomes idle until the relevant data is transferred to the buffer memory. In order to prefetch the memory access to be performed, a means for detecting the two cases described above and a means for switching between the two cases are provided, and the prefetch operation corresponding to each case is controlled to be performed. This has the effect of maximizing the functionality and improving the throughput of the data processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram illustrating a conventional prefetch operation. In the drawing, 1 is an instruction control unit (IU), 2, 7.12 is a selector. 3 is the execution address register (EAR). 4 is a tag section (TAG), 5 is a match detection circuit (M
CH). 6 is a buffer memory (BS). 8 is an instruction word register (IWR). 9 is an operand word register (OWR). 10 is an arithmetic unit (EU), 11 is an adder (ING
). 13 is a real address register (RAR). 14 is a main memory address register (MSAR). 15 is a main memory unit (MCU). 16 is prefetch bo) (PF PORT). 17 is a memory access type detection unit (MAFDET). S is a selector control signal. are shown respectively.

Claims (1)

[Claims] A data processing device having a buffer memory and a block-by-block prefetch function for the buffer memory, and a first means for detecting an instruction fetch or an operand fetch of consecutive addresses when the memory control unit is accessed from the instruction control unit. and a second means for detecting an operand fetch of a discontinuous address, and when the main memory is accessed and the memory access detected by the first means is detected, one block worth of data is added to the access address. Prefetch is performed using the address obtained by adding the addresses of
A data processing device characterized by having a function of prefetching a memory access subsequent to the memory access detected by the second means.