JPH11338774A - Information processor, its system bus optimizing method and recording medium recording control program therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor with which the processing performance of a system is improved and more efficient data transfer can be provided. SOLUTION: A bus connector 3 connects a system bus 100, to which a central processing unit 1 and a main storage device 2 are connected, to an I/O bus 200 to which a bus extension device 4 is connected. The bus extension device 4 is a device for extending an extension I/O bus 300 from the I/O bus 200 and provided with a cache control part 41 and a cache part 42. The cache control part 41 holds a flag showing whether data held in the cache part 42 are valid or not and the address of data held in the cache part 42 on the main storage device 2 and when valid data exist in the cache part 42, corresponding to read requests from input/output devices 5-1 to 5-6 to the main storage device 2, data in the cache part 42 are responded as read data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, a system bus optimizing method therefor, and a recording medium storing a control program therefor, and more particularly to an information processing apparatus in which a plurality of input / output devices are connected via a bus connection device. About.

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus of this kind, an I / O (Input / O / O) connected to a bus connecting device is used.
In some cases, a bus expansion device is connected to an output bus, and a plurality of input / output devices are connected to an expansion I / O bus connected to the bus expansion device. The bus connection device connects the system bus and the I / O bus, and a central processing unit, a main storage device, and the like are connected on the system bus.

In the above configuration, when each of the plurality of input / output devices accesses the main storage device via the expansion I / O bus, the bus expansion device, the I / O bus, the bus connection device, and the system bus, (Hereinafter referred to as a system bus cycle) must be started. At this time, a system bus cycle for the central processing unit to access the main storage device is waited.

As an extended system as described above, there is a technique disclosed in Japanese Patent Application Laid-Open No. 5-242232.
According to the technology described in this publication, a local bus is provided on a board, and input means from a video device, display memory means, image data compression / expansion means,
(Personal computer) and an interface means with an extended I / O bus.

In this case, the local bus is connected to the PC via the interface means, and data is exchanged between the PC and the other means on the local bus through the local bus and the interface means. Therefore, it is easy to remove each unit from the local bus or to add a device that realizes another function to the local bus.

[0006] In addition to the above system, Japanese Unexamined Patent Application Publication No.
There is a technique disclosed in -128346. In the technique described in this publication, first and second bus bridges are connected to a lower bus to which a main memory and an I / O device are connected, and the first and second bus bridges are connected to the first and second bus bridges, respectively. A plurality of CPUs (Central Processing Units) are connected to the second upper bus, respectively.

[0007] The first and second bus bridges are connected to first and second bridge caches respectively shared by a plurality of CPUs. Each of the first and second upper buses is used as a split bus. Are split-compatible. By adopting such a configuration, the number of CPUs that can be connected can be increased by layering, and by adopting a bridge cache and splitting the upper bus, degradation of throughput and latency due to layering can be prevented. .

[0008]

In the conventional information processing apparatus described above, when each of a plurality of input / output devices accesses the main storage device, it is necessary to start a system bus cycle. When the access to the device frequently occurs, a load is applied to the system bus, a cycle for the central processing unit to access the main storage device is waited, and the processing performance of the system is reduced.

An object of the present invention is to solve the above problems, improve the processing performance of a system, and realize an information processing apparatus capable of realizing more efficient data transfer and a system bus optimization thereof. An object of the present invention is to provide a recording medium recording a method and a control program thereof.

[0010]

An information processing apparatus according to the present invention connects a system bus to which a central processing unit and a main storage device are connected to an input / output bus by a bus connection device, and a plurality of input / output devices are connected. An information processing device for connecting the expanded input / output bus to the input / output bus by a bus expansion device, wherein the cache unit stores a part of data stored in the main storage device, and the plurality of input / output devices And control means for controlling when the data corresponding to the read request from any one of the above is stored in the cache means, reads the data from the cache means and outputs the data to the request source. .

According to a method of optimizing a system bus of an information processing device according to the present invention, a system bus to which a central processing unit and a main storage device are connected and an input / output bus are connected by a bus connection device, and a plurality of input / output devices are connected. A bus expansion device for connecting the expanded I / O bus to the I / O bus, the system bus optimization method for an information processing device, wherein one of data provided in the bus expansion device and stored in the main storage device is provided. Determining whether or not data corresponding to a read request from any of the plurality of input / output devices is stored in the cache unit that stores the data, and determining whether the data is stored. Reading the data from the cache means and outputting the data to the request source.

A recording medium storing a system bus optimization control program for an information processing apparatus according to the present invention includes a system bus to which a central processing unit and a main storage device are connected, and an input / output bus connected by a bus connection device. System bus optimization control program for causing the bus expansion device to optimize the system bus in an information processing device that connects the expansion input / output bus connected to the input / output device to the input / output bus with the bus expansion device Is a recording medium on which
The system bus optimization control program may be provided in the bus expansion device from a cache unit provided in the bus expansion device and storing a part of data stored in the main storage device from any of the plurality of input / output devices. It is determined whether data corresponding to the read request is stored, and when it is determined that the data is stored, the data is read from the cache unit and output to the request source.

That is, the information processing apparatus according to the present invention has an input / output bus [I / O (Ipu) that connects a system bus to which a central processing unit and a main storage device are connected and a bus expansion device.
t / Output) bus] with a bus connection device,
Extended I / O bus (extended I / O) to which the bus extension device is connected
In a system in which a plurality of input / output devices are connected to a bus, a cache function (cache control unit and cache unit) for caching data in a main storage unit is provided in a bus expansion device.

This eliminates the necessity of starting the system bus cycle when the input / output device connected to the extended I / O bus accesses the main storage device, so that the central processing unit can access the main storage device. Waiting for a system bus cycle is reduced, and the processing performance of the system is improved.

Further, when a bus expansion device is connected to an existing main system, there is no need to cope with the main system, so that the cache function can cope with a plurality of addresses, thereby increasing efficiency. Data transfer can be realized.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an information processing apparatus according to one embodiment of the present invention. In the figure, an information processing apparatus according to an embodiment of the present invention includes a central processing unit 1, a main storage device 2, a bus connection device 3, a bus expansion device 4, and input / output devices 5-1 to 5-6. It is configured.

The central processing unit 1 is a device for performing arithmetic processing.
The microinstructions stored in the main storage device 2 are sequentially read and executed. Further, the central processing unit 1 includes input / output devices 5-1 to 5-1.
When performing input / output processing for any of 5-6, input / output instructions are stored in the main storage device 2, and the input / output devices 5-1 to 5-
Issue an input / output instruction to the device # 6.

The main storage device 2 is connected to the central processing unit 1 and the bus connecting device 3 via the system bus 100, and sends out data in accordance with a data read request from the central processing unit 1 and the bus connecting device 3. Central processing unit 1
And holds data in accordance with a data write request from the bus connection device 3.

The bus connection device 3 is a device for connecting the system bus 100 to which the central processing unit 1 and the main storage device 2 are connected, and the I / O bus 200 to which the bus expansion device 4 is connected.

The bus expansion device 4 is a device for expanding the expansion I / O bus 300 from the I / O bus 200, and includes a cache control unit 41 and a cache unit 42. The cache control unit 41 includes a flag indicating whether data held in the cache unit 42 is valid or invalid and a flag indicating whether the data is valid or invalid.
And the address of the data stored in the main storage device 2. When valid data exists in the cache unit 42 in response to a read request from the input / output devices 5-1 to 5-6 to the main storage device 2, the cache control unit 41 converts the data in the cache unit 42 into read data. To respond.

FIG. 2 is a flowchart showing the control of the cache control unit 41 when issuing an I / O instruction from the central processing unit 1 to the I / O devices 5-1 to 5-6 in FIG. 1, and FIG. 3 and FIG. 6 is a flowchart showing control of the cache control unit 41 in a read cycle and a write cycle of the input / output devices 5-1 to 5-6 in FIG.

The operation of the information processing apparatus according to one embodiment of the present invention will be described with reference to FIGS. still,
The processing shown in FIGS. 2 to 4 is realized by causing the cache control unit 41 of the bus expansion device 4 to execute a program recorded in a control memory (not shown). A ROM (Read Only Memory), a floppy disk, or the like connected to any of the I / O buses 300 can be used.

When the central processing unit 1 issues an input / output command to the input / output device 5-1, an input / output command program is stored in the main storage device 2. At this time, the cache control unit 41 of the bus expansion device 4 determines that the command input via the system bus 100, the bus connection device 2, and the I / O bus 200 is an input / output command for the input / output device 5-1. Upon detection (step S1 in FIG. 2), the instruction is output to the input / output device 5-1 via the extended I / O bus 300 (step S2 in FIG. 2).

Thereafter, the cache control unit 41 detects that there is data (input / output instruction program) accompanying the instruction (step S3 in FIG. 2), and if the data is not in the cache unit 42 (step S4 in FIG. 2). ), And stores the data in the cache unit 42 to make the cache valid / invalid flag valid (step S5 in FIG. 2).

When an input / output command from the central processing unit 1 is input via the bus expansion device 4 and the expansion I / O bus 300, the input / output device 5-1 reads the input / output command program from the main storage device 2. A bus cycle of the extended I / O bus 300 is generated.

When the cache control unit 41 of the bus expansion unit 4 receives a bus cycle for reading an input / output instruction program from the input / output unit 5-1 (step S1 in FIG. 3).
1) If the input / output instruction program is stored in the cache unit 42 (step S12 in FIG. 3) and the cache valid / invalid flag of the input / output instruction program is valid (step S13 in FIG. 3), the I / O bus I / O device 5-1 without causing a bus cycle to
Sends the input / output instruction program (read data) stored in the cache unit 42 to the server (step S14 in FIG. 3).

The cache control unit 41 executes the above processing until the bus cycle for reading the input / output instruction program from the input / output device 5-1 ends (step S3 in FIG. 3).
11 to S15).

On the other hand, the cache control unit 41 determines whether the input / output instruction program is not stored in the cache unit 42 (step S12 in FIG. 3) or if the cache valid / invalid flag of the input / output instruction program is invalid. (Step S13 in FIG. 3), the input / output instruction program is read from the main storage device 2 (Step S16 in FIG. 3).

The cache control unit 41 sends the input / output instruction program read from the main storage device 2 to the input / output device 5-1, and stores the input / output instruction program in the cache unit 42 to enable / disable the cache. The invalid flag is made valid (step S17 in FIG. 3).

The above operation describes a read cycle of the input / output device 5-1 when the central processing unit 1 issues an input / output command to the input / output device 5-1. On the other hand, when the cache control unit 41 receives a bus cycle for writing data from the input / output device 5-1 to the main storage device 2 (step S18 in FIG. 4), the cache control unit 41 caches the data from the input / output device 5-1. It is stored in the section 42 (step S19 in FIG. 4).

The cache control unit 41 executes the above processing until a bus cycle for writing data from the input / output device 5-1 to the main storage device 2 ends (steps S19 and S20 in FIG. 4).

Thereafter, when the system bus 100 is free (step S21 in FIG. 4), the cache control unit 41
The data stored in the cache unit 42 is written to the main storage device 2 (step S22 in FIG. 4), and the cache valid / invalid flag of the data is invalidated (step S2 in FIG. 4).
3).

In the above-described processing, the processing for the input / output device 5-1 has been described, but the other input / output devices 5-2 to 5-
6 can be processed in the same manner as the input / output device 5-1. In order to invalidate the data stored in the cache unit 42 in the bus expansion device 4, the cache valid / invalid flag in the cache control unit 41 is invalidated.

As described above, by caching a part of the data stored in the main storage device 2 in the cache unit 42 under the control of the cache control unit 41 in the bus expansion device 4, the When the connected input / output devices 5-1 to 5-6 access the main storage device 2, there is no need to activate a system bus cycle.

Therefore, when the input / output devices 5-1 to 5-6 access the main storage device 2, it is not necessary to activate the system bus cycle.
Waiting for a system bus cycle to access the system can be reduced, and the processing performance of the system can be improved.

Further, when the bus expansion device 4 is connected to the existing main system, there is no need to cope with the main system, so that the cache unit 42 can cope with a plurality of addresses. Thus, more efficient data transfer can be realized.

[0037]

As described above, according to the present invention, a system bus to which a central processing unit and a main storage device are connected and an input / output bus are connected by a bus connection device, and a plurality of input / output devices are connected. In an information processing apparatus for connecting an extended I / O bus to an I / O bus by a bus extension device, a cache means for storing a part of data stored in a main storage device, and a read from one of a plurality of I / O devices Improving the processing performance of the system by providing, in the bus expansion device, control means for controlling the data read from the cache means and outputting the data to the request source when the data corresponding to the request is stored in the cache means. Thus, there is an effect that more efficient data transfer can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating control of a cache control unit when an I / O instruction is issued from the central processing unit to the I / O device in FIG. 1;

FIG. 3 is a flowchart showing control of a cache control unit in a read cycle and a write cycle of the input / output device of FIG. 1;

FIG. 4 is a flowchart showing control of a cache control unit in a read cycle and a write cycle of the input / output device of FIG. 1;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 central processing unit 2 main storage device 3 bus connection device 4 bus expansion device 5-1 to 5-6 input / output device 41 cache control unit 42 cache unit 100 system bus 200 I / O bus 300 expansion I / O bus

Claims (12)

[Claims] An input / output bus is connected to a system bus to which a central processing unit and a main storage device are connected by a bus connection device, and an expansion input / output bus to which a plurality of input / output devices are connected is connected by a bus expansion device. An information processing device connected to a writing output bus, wherein a cache means for storing a part of data stored in the main storage device, and data corresponding to a read request from any of the plurality of input / output devices are An information processing apparatus comprising: a bus expansion device; and a control unit that controls the data to be read from the cache unit and output to a request source when the data is stored in the cache unit. 2. The data processing apparatus according to claim 1, wherein the control unit stores data associated with an input / output instruction from the central processing unit to the input / output device in the cache unit when the data is stored in the main storage device. The information processing apparatus according to claim 1, wherein: 3. The control unit according to claim 1, wherein when there is data to be written from said input / output device to said main storage unit, said data is stored in said cache unit and then written to said main storage unit. The information processing apparatus according to claim 1 or 2, wherein 4. The system according to claim 1, wherein the control unit writes data to the main storage device when data to be written to the main storage device exists in the cache unit and the system bus is free. 4. The information processing apparatus according to claim 3, wherein: 5. An I / O bus is connected to a system bus to which a central processing unit and a main storage device are connected by an I / O bus, and an I / O bus to which a plurality of I / O devices are connected is connected by a bus expansion device. A method of optimizing a system bus of an information processing device connected to a writing output bus, wherein the plurality of input / output devices are provided in a cache unit provided in the bus expansion device and storing a part of data stored in the main storage device. Determining whether or not data corresponding to a read request from any of the devices is stored; and when it is determined that the data is stored, the data is read from the cache unit and output to the request source. And a step of performing the above operation in the bus expansion apparatus. 6. The bus expansion device includes a step of storing data associated with an input / output instruction from the central processing unit to the input / output device in the cache unit when the data is stored in the main storage device. 6. The system bus optimizing method according to claim 5, wherein: 7. The bus expansion device according to claim 1, wherein when there is data to be written from said input / output device to said main storage device, said data is stored in said cache means and then written to said main storage device. The system bus optimizing method according to claim 5 or 6, wherein: 8. The step of writing data from the input / output device to the main storage device includes the step of writing the data to the main storage device when the data to be written to the main storage device is present in the cache unit and the system bus is free. The system bus optimizing method according to claim 7, wherein is written in said main storage device. 9. An I / O bus is connected to a system bus to which a central processing unit and a main storage device are connected, and an extended I / O bus to which a plurality of I / O devices are connected by a bus extension device. A recording medium recording a system bus optimization control program for causing the bus expansion device to optimize the system bus in an information processing device connected to a writing output bus, wherein the system bus optimization control program is Data corresponding to a read request from any of the plurality of input / output devices is stored in a cache unit provided in the bus expansion device and storing a part of data stored in the main storage device. It is determined whether or not the data is stored. When it is determined that the data is stored, the data is read from the cache unit and output to the request source. A recording medium on which a system bus optimization control program is recorded. 10. The system bus optimization control program, when data associated with an input / output instruction from the central processing unit to the input / output device is stored in the main storage device, stores the data in the bus expansion device. 10. A recording medium storing a system bus optimization control program according to claim 9, wherein said recording medium is stored in a cache means. 11. The system bus optimization control program stores data in the bus expansion device when the data to be written from the input / output device to the main storage device is stored in the cache unit, and then stores the data in the main storage device. 11. A recording medium on which a system bus optimization control program according to claim 9 or 10 is written. 12. The system bus optimization control program, when causing the bus expansion device to write data from the input / output device to the main storage device, stores the data to be written to the main storage device in the cache. 12. The recording medium according to claim 11, wherein said data is written to said main storage device when said system bus is available and said system bus is free.