JP2000029788A - Cache memory system, cache control method used therefor and recording medium control program therefor recorded therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache memory system, capable of accelerating a cache error processing at writing of the large amount of data to successive addresses and accelerating the execution speed of a software including the cache error processing. SOLUTION: A normal write instruction (write and storage) 11, corresponding to a conventional cache control method and the write instruction 12 for a cache error are respectively prepared as being different instructions in the instruction set 10 of a general purpose processor 1. When the processing of the cache error is required, the write instruction 12 for the cache error updates a cache line 27 by write data, without reading the data from the address of a main memory 21 equivalent to a write address and sets both of the V-bit 24 and M-bit 25 of the line 27 to '1'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system, a cache control method used therefor, and a recording medium on which a control program is recorded. About.

[0002]

2. Description of the Related Art At present, multimedia processing is required in various information devices, from inexpensive consumer electronics products such as video game consoles and Internet terminals to relatively high performance products such as car navigation systems and personal computers. I have. Multimedia processing used in these devices includes compression and decompression of audio, audio, and video signals, and two-dimensional and three-dimensional graphics processing. In such multimedia processing, it is necessary to perform many operations on a huge amount of data.

Conventionally, in the above multimedia processing, in addition to a general-purpose processor for controlling the entire apparatus and a user interface, an LSI (large-scale integrated circuit) dedicated to specific multimedia processing is incorporated in the apparatus.
It has met the demand for processing power.

However, recently, with the improvement in performance of general-purpose processors, multimedia processing can be performed at a sufficient speed by software on the general-purpose processor without incorporating a dedicated LSI.

[0005] If the dedicated LSI is replaced with multimedia processing software on a general-purpose processor, additional hardware such as a dedicated LSI becomes unnecessary, so that the equipment can be configured at low cost and its function can be easily realized by changing the software. can do. For example, audio expansion and video signal expansion can be switched by changing software.

As described above, multimedia processing by software has many advantages. Therefore, even if the current general-purpose processor has insufficient processing capability, an operation instruction dedicated to multimedia processing is introduced into the general-purpose processor in order to cover the application with software processing. However, it is also common to improve multimedia processing performance.

[0007] Regarding the multimedia processing instruction as described above, see "VIS Speeds New Media."
Processing, "(Marc Trembla
y, et al., IEEE Micro, pp. 10-26. 10-20, A
ug. 1996), “Intel's MMX Spe
eds Multimedia "(Linley Gwe
nnap, Microprocessor Reporter
t, Vol. 10, No. 3, pp. 1,6-10, M
ar. 5, 1996), “NEC V830R / AV
Handles Real-Time MPEG-2 "
(JimTurley, Microprocessor
Report, Vol. 11, No. 12, pp.
5, Sep. 15, 1997).

[0008] The instruction set dedicated to multimedia processing described in the above-mentioned paper divides a register and stores a plurality of data, and performs a parallel operation with one instruction, so that the processing capability in processing with high data parallelism is achieved. Has been improved. For example, four 16-bit data are stored in a 64-bit register, and four parallel operations can be performed on these data with one instruction. An operation instruction using such data parallelism is hereinafter referred to as SIMD (Single-Instruction).
It is called an “ion Multiple-Data” instruction.

In order to efficiently perform multimedia processing by a general-purpose processor, the SIMD instruction is introduced to enhance the computing capacity, and at the same time, the memory system is strengthened so that the data on the memory system can be processed at a rate corresponding to the computing capacity. It is important that the data after the calculation be stored in the memory system.

The configuration of a typical memory system 2 of a system using the general-purpose processor 5 and the operation at the time of data access will be described with reference to FIGS. As shown in FIG. 4, the memory system 2 connected to the general-purpose processor 5 is configured by combining a large-capacity main memory 21 and a high-speed cache memory 22, and a memory that controls the main memory 21 and the cache memory 22. Control circuit 20
It has.

[0011] Of the data stored in the main memory 21, a copy of some frequently accessed data is stored in the cache memory 22, and when the general-purpose processor 5 performs data access, the target data is stored in the cache memory 22. If data exists, control is performed so as to access the high-speed cache memory 22 instead of the low-speed main memory 21, thereby improving the execution speed of the program.

The cache memory 22 is normally divided into several hundred to several thousand lines 27, and control information is added to each line 27 to manage the state. The size of data held by one line 27 is generally 16 to 64 bytes. As control information, data 2 held in each line 27
6, a tag 23 indicating upper bits of an address on the main memory 21, a valid (V) bit 24 indicating that the data 26 is valid, and a modify (M) bit 25 indicating that the data 26 has been updated. Is added.

The V bit 24 is the data 2 of the line 27
6 indicates valid or invalid. Hereinafter, the V bit 24 is set to "1".
, The data 26 of the line 27 is made valid,
When it is “0”, the data 26 is invalidated.

The M bit 25 is the data 2 of the line 27.
6 has been updated and whether the data 26 in the cache memory 22 is newer than the data in the main memory 21 or not updated and the data 26 in the cache memory 22 is equal to the data in the main memory 21. Show. Hereinafter, when the M bit is "1", the data 26 in the cache memory 22 is assumed to be newer than the data in the main memory 21. When the M bit is "0", the data 26 in the cache memory 22 is equal to the data in the main memory 21. Shall be.

As shown in FIG. 4, the general-purpose processor 5 and the cache memory 22 have logically independent functions, but when physically integrated on the same LSI chip, they are separate chips. There are cases in which they are incorporated in the same multichip module or cartridge.

In the example shown in FIG.
The cache memory 22 existing between the main memory 21 and the main memory 21 has one stage, but the cache memory 22 may have multiple stages in order to configure a higher-performance memory system 2.

The control of the cache memory 22 during data reading will be described with reference to FIG. It is assumed that the general-purpose processor 5 requests the cache memory 22 to read the data at the address Ar. Memory control circuit 20
Searches the line 27 having the same value of the tag 23 as the upper bit of the address Ar (step S11 in FIG. 5).

Tag 23 which is the same as the upper bit of address Ar
And a line 27 having the value of
Then, the memory control circuit 20 calculates the V bit 2 of the line i.
4 (step S12 in FIG. 5). If the V bit 24 is "1", since the line i contains the target data (cache hit), the required portion of the data 26 of the line i is It returns to the general-purpose processor 5 (step S13 in FIG. 5).

The address Ar is stored in the cache memory 22.
When there is no line having the same value of the tag 23 as the upper bit of, or when the V bit 24 is “0” even if it exists,
Since the target data does not exist in the cache memory 22 (cache miss), the memory control circuit 20 selects an appropriate line (referred to as line j) (step S5 in FIG. 5).
14) The data at the address Ar on the main memory 21 is copied to the line j (step S18 in FIG. 5).

However, the memory control circuit 20 checks the V bit 24 and the M bit 25 of the selected line j (steps S15 and S16 in FIG. 5), and when both are "1", the line j is newer than the main memory 21. Since the data is held, the data on line j is written back to the corresponding address in the main memory 21 (step S1 in FIG. 5).
7) The data at address Ar is copied to line j (step S18 in FIG. 5).

Thereafter, the memory control circuit 20 sets the V bit 2
4 is set to "1" and the M bit 25 is set to "0" (step S19 in FIG. 5), indicating that the line j holds a valid copy of the data in the main memory 21, and the data of the line j Is returned to the general-purpose processor 5 (step S20 in FIG. 5). At this time, the value j of the line 27
Usually, is appropriately selected depending on the value of the address Ar and the usage status of each line. However, since the method is known, detailed description thereof will be omitted.

Next, control of the cache memory 22 during data write will be described with reference to FIG. Here, a cache control method called a write-back method will be particularly described. This data write is executed by a write instruction (write, store) 51 included in the instruction set 50 in the general-purpose processor 5.

From the general-purpose processor 5 to the cache memory 2
Assume that there is a write request for the data of the address Aw in No. 2. The memory control circuit 20 searches for the line 27 having the same value of the tag 23 as the upper bit of the address Aw (step S31 in FIG. 6).

Tag 23 same as upper bits of address Aw
Is present in the cache memory 22 and the line is a line i, the memory control circuit 2
0 checks the V bit 24 of the line i (step S3 in FIG. 6).
2) If the V bit 24 is "1", since the line i contains the target data (cache hit), the data on the line i is rewritten (step S33 in FIG. 6). Further, the memory control circuit 20 sets the M bit of the line i to "1" (step S34 in FIG. 6), and the main memory 21
This indicates that the data on the cache line i is newer than the above data.

The address Aw is stored in the cache memory 22.
When there is no line having the same tag value as the upper bit of, or when the V bit 24 is "0", the target data does not exist in the cache memory 22 (cache miss). The circuit 20 selects an appropriate line (line j) (step S3 in FIG. 6).
5) The data at the address Aw on the main memory 21 is copied to the line j (step S39 in FIG. 6).

However, the memory control circuit 20 checks the V bit 24 and the M bit 25 of the selected line j (steps S36 and S37 in FIG. 6). When both are "1", the line j is newer than the main memory 21. Since the data is held, the data of the line j is written back to the corresponding address of the main memory 21 (step S3 in FIG. 6).
8) Copy the data at address Aw to line j (step S39 in FIG. 6).

Thereafter, the memory control circuit 20 updates the data of the line j (step S40 in FIG. 6) and
Bit 24 and M bit 25 are both set to "1" (FIG. 6
Step S41) indicates that valid data exists on line j of the cache memory 22, and that the data on line j of the cache memory 22 is newer than the data on the main memory 21. As in the case of a read cache miss, the value j of the line 27 is usually appropriately selected depending on the value of the address Aw and the usage status of each line. However, since the method is known, detailed description thereof is omitted. I do.

When a write cache miss occurs, address A
Reading the value in w into the cache memory 22 once means that the data to be rewritten at one time is
Because it is only part of it. One line of the cache typically holds 16-64 bytes of data, while a single data write instruction typically writes 1-8 bytes of data. Of the data of the cache line j, the data not updated by the data write is stored in the main memory 2
If it does not match the value of the corresponding data on 1, the consistency cannot be maintained.

[0029]

Generally, in multimedia processing, a large amount of calculation results are often written to consecutive addresses. For example, a video image compression standard I
TU-T Recommendation H. 261, H .; 262, H .; 263, M
PEG (Moving Picture Expert)
s Group) -1 video (ISO / IEC1117)
2. “Information Technology”
-Coding of Moving Picture
s and Associated Audio fo
r Digital Storage Media u
p to 1.5 Mbit / s ”), MPEG-2 video (ISO / IEC13818-2,“ Informat
ion Technology-Generic Co
ding of of Moving Picture
When a video image is reproduced by expanding a bit stream compressed according to “s and Associated Audio”), the reproduced image is written into a frame buffer secured on a main memory.

For example, MPEG-2 Main Lev
720 × 480 which is a resolution generally used for EL
When a pixel image is expanded, a continuous area of 345,600 bytes is included in a luminance signal per picture by a color difference signal 2.
A continuous area of 86,400 bytes for each sheet is secured on the main memory.

That is, a memory amount of 506 Kbytes per picture is required. To implement the bidirectional motion prediction used in MPEG-2, it is necessary to hold at least three pictures, so that the working area of the MPEG-2 video decompression software requires at least 1.5 Mbytes. The capacity of the cache memory is usually several tens to several hundreds of Kbytes, and it is not possible to hold all of this amount of data. Therefore, data cache misses frequently occur in frame buffer access, and high-speed MPEG-
2 It is an obstacle for creating video decompression software.

Further, in order to reproduce 30 images per second in real time, it is necessary to write 14.8 Mbytes of data per second to the main memory. Considering that this writing causes a data cache miss, in order to maintain consistency between the cache memory and the main memory, the same amount of data is read from the main memory to the cache memory before writing the decompressed data. Because this 2
That is, data access of 29.6 Mbytes / sec occurs to the main memory. This amount is, for example, one of the bandwidth of the bus operating at 32 bits and 66 MHz.
It reaches 1.5% and cannot be ignored due to its processing performance.

FIG. 7 shows the exchange of data between the cache memory and the main memory when data is written to consecutive addresses, and changes in data on the cache memory and the main memory.

As a typical example, assume that the data size of one line of the cache is 16 bytes and the size of data to be written is 4 bytes. Here, four 4-byte data N0, N1, N from the address Aw of the main memory
Consider a case where 2 and N3 are written one by one.

Further, it is assumed that the data of the address Aw does not initially exist in the cache memory, and the address Aw
The cache line i holding the data of
It is assumed that 0, U1, U2, and U3 are stored.

First, the operation when the value N0 is written to the address Aw will be considered. When a write request of the value N0 to the address Aw occurs (see (11) in FIG. 7), a cache miss occurs because the data of the address Aw does not exist in the cache memory, and the address Aw on the main memory starts. Data M0, M1, M for 16 bytes per line
2, M3 (see 47 in FIG. 7) is read into cache line i [see (17) and 42 in FIG. 7]. afterwards,
M0 corresponding to the data of 4 bytes from the address Aw in the data of the line i is overwritten by N0 [see (12) and 43 in FIG. 7].

Next, 4-byte data N1 is written to the adjacent address Aw + 4 [see (13) in FIG. 7]. Since data of 16 bytes per line from the address Aw exists in the cache memory, this write hits the cache, and updates the data corresponding to the address Aw + 4 on the line i to N1 (see 44 in FIG. 7).

Third, at the adjacent address Aw + 8,
The 4-byte data N2 is written [(14) in FIG.
reference]. Since data of 16 bytes per line from the address Aw exists in the cache memory, this write hits the cache and the address Aw + 8 on the line i
Is updated to N2 [see 45 in FIG. 7].

Finally, at the adjacent address Aw + 12,
The 4-byte data N3 is written [(15) in FIG.
reference]. Since data of 16 bytes per line from the address Aw exists in the cache memory, this write hits the cache and the address Aw + 1 on the line i
The data corresponding to 2 is updated to N3 [see 46 in FIG. 7].

As described above, all the data on the cache line i has been rewritten by the writing of N0, N1, N2, and N3, and are newer than the data 47 of 16 bytes per line from the address Aw on the main memory. Therefore, when data of another address is stored in the line i, it is necessary to first write the data of the line i back to the main memory [see (16) and 48 in FIG. 7].

Therefore, an object of the present invention is to solve the above-mentioned problems and to speed up a cache miss process when writing a large amount of data to a continuous address. The present invention provides a cache memory system capable of improving the execution speed of a cache memory, a cache control method used for the same, and a recording medium recording the control program.

[0042]

A cache memory system according to the present invention is a cache memory system including a main memory and a cache memory for holding a part of data stored in the main memory. Selecting means for selecting an address of the cache memory for storing data of the write cache when a write cache miss occurs, and validity or invalidity of the data of the cache memory corresponding to the address selected by the selection means Determining means for determining whether or not the data at the time of the write cache is read by the selecting means without reading data of the main memory corresponding to the data into the cache memory when the determining means determines that the data is invalid. Writing means for writing to the selected address. To have.

A cache control method according to the present invention is a cache control method for a cache memory system including a main memory and a cache memory for holding a part of data stored in the main memory, wherein the write to the cache memory is performed. Selecting an address of the cache memory for storing the data of the write cache when a cache miss occurs; and determining whether the data of the cache memory corresponding to the selected address is valid or invalid. Writing the data at the time of the write cache to an address selected by the selection means without reading the data of the main memory corresponding to the data into the cache memory when the data is determined to be invalid. Have.

A recording medium on which the cache control program according to the present invention is recorded is a recording medium on which a cache control program for causing a computer to control a cache memory that holds a part of data stored in a main memory is recorded. The cache control program causes the computer to select an address of the cache memory for storing data of the write cache when a write cache miss occurs in the cache memory, and the cache corresponding to the selected address Determining whether the data in the memory is valid or invalid; and when the data is determined to be invalid, selecting the data in the write cache without reading the data in the main memory corresponding to the data into the cache memory. Selected by And then written to the address.

That is, the cache memory system of the present invention comprises: a data; a tag indicating the upper bit of an address of the retained data in the main memory; a valid (V) bit indicating that the data is valid; And a plurality of cache lines including a modify (M) bit indicating that the data has been updated.

In the cache memory system of the present invention, at the time of writing to the cache memory, there is no line in the cache that has a tag that matches the upper bit of the write address and the V bit is "1". When it is necessary to process a miss, without reading data from the main memory address corresponding to the write address,
The cache line is updated with the write data, and both the V bit and the M bit are set to "1".

Therefore, the time for reading data from the address of the main memory can be reduced. Therefore, it is possible to speed up cache miss processing when writing a large amount of data to consecutive addresses, and to improve the execution speed of software including the cache miss processing.

[0048]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a cache memory system according to one embodiment of the present invention. In the figure, a cache memory system according to one embodiment of the present invention includes a general-purpose processor 1 and a memory system 2 connected to the general-purpose processor 1.

The general-purpose processor 1 issues a write instruction (write,
It has an instruction set 10 including a (store) 11 and a write instruction 12 for cache miss, and reads / writes data stored in the memory system 2 when executing software.
The instruction set 10 can be stored in a ROM (Read Only Memory), an IC (Integrated Circuit) memory, or the like.

The memory system 2 is configured by combining a large-capacity main memory 21 and a high-speed cache memory 22, and includes a memory control circuit 20 for controlling the main memory 21 and the cache memory 22.

The cache memory 22 is divided into several hundred to several thousand lines 27, and control information is added to each line 27 to manage the state. The size of data held by one line 27 is 16 to 64 bytes.

As the control information, a tag 23 indicating an upper bit of an address of the held data 26 on the main memory 21 and a valid (V) bit 24 indicating that the data 26 is valid for each line 27. And a modify (M) bit 25 indicating that the data 26 has been updated.

The V bit 24 is the data 2 of the line 27
6 indicates valid or invalid. Hereinafter, the V bit 24 is set to "1".
, The data 26 of the line 27 is made valid,
When it is “0”, the data 26 is invalidated.

The M bit 25 is the data 2 of the line 27.
6 has been updated and whether the data 26 in the cache memory 22 is newer than the data in the main memory 21 or not updated and the data 26 in the cache memory 22 is equal to the data in the main memory 21. Show. Hereinafter, when the M bit is "1", the data 26 in the cache memory 22 is assumed to be newer than the data in the main memory 21. When the M bit is "0", the data 26 in the cache memory 22 is equal to the data in the main memory 21. Shall be.

In the embodiment of the present invention, the operation at the time of data reading is the same as that of the prior art shown in FIG. That is, it is assumed that the general processor 1 requests the cache memory 22 to read the data at the address Ar. The memory control circuit 20 searches for the line 27 having the same value of the tag 23 as the upper bit of the address Ar (Step S in FIG. 5).
11).

Tag 23 same as upper bit of address Ar
And a line 27 having the value of
Then, the memory control circuit 20 calculates the V bit 2 of the line i.
4 (step S12 in FIG. 5). If the V bit 24 is "1", since the line i contains the target data (cache hit), the required portion of the data 26 of the line i is This is returned to the general-purpose processor 1 (step S13 in FIG. 5).

The address Ar is stored in the cache memory 22.
When there is no line having the same value of the tag 23 as the upper bit of, or when the V bit 24 is “0” even if it exists,
Since the target data does not exist in the cache memory 22 (cache miss), the memory control circuit 20 selects an appropriate line (referred to as line j) (step S5 in FIG. 5).
14) The data at the address Ar on the main memory 21 is copied to the line j (step S18 in FIG. 5).

However, the memory control circuit 20 checks the V bit 24 and the M bit 25 of the selected line j (steps S15 and S16 in FIG. 5). When both are "1", the line j is newer than the main memory 21. Since the data is held, the data on line j is written back to the corresponding address in the main memory 21 (step S1 in FIG. 5).
7) The data at address Ar is copied to line j (step S18 in FIG. 5).

Thereafter, the memory control circuit 20 sets the V bit 2
4 is set to "1" and the M bit 25 is set to "0" (step S19 in FIG. 5), indicating that the line j holds a valid copy of the data in the main memory 21, and the data of the line j Is returned to the general-purpose processor 1 (step S20 in FIG. 5). At this time, the value j of the line 27
Usually, is appropriately selected depending on the value of the address Ar and the usage status of each line. However, since the method is known, detailed description thereof will be omitted.

FIG. 2 is a flowchart showing the operation at the time of data writing according to one embodiment of the present invention. The operation at the time of data write according to one embodiment of the present invention will be described with reference to FIGS.

From the general-purpose processor 1 to the cache memory 2
Assume that there is a write request for the data of the address Aw in No. 2. The memory control circuit 20 searches for a line 27 having the same value of the tag 23 as the upper bit of the address Aw (step S1 in FIG. 2).

Tag 23 same as upper bit of address Aw
And a line 27 having the value of
Then, the memory control circuit 20 calculates the V bit 2 of the line i.
4 (step S2 in FIG. 2), and the V bit 24 is "1".
If so, since the line i contains the target data (cache hit), the data on the line i is rewritten (step S3 in FIG. 2). Further, the memory control circuit 20 sets the M bit of the line i to "1" (step S2 in FIG. 2).
4) indicates that the data on the cache line i is newer than the data on the main memory 21.

The address Aw is stored in the cache memory 22.
When there is no line having the same value of the tag 23 as the upper bit of, or when the V bit 24 is “0” even if it exists,
Since the target data does not exist in the cache memory 22 (cache miss), the memory control circuit 20 selects an appropriate line (line j) (step S2 in FIG. 2).
5) Then, data is written to line j (step S9 in FIG. 2).

However, the memory control circuit 20 checks the V bit 24 and the M bit 25 of the selected line j (steps S6 and S7 in FIG. 2). When both are "1", the line j is newer than the main memory 21. Since the data is held, the data on line j is written back to the corresponding address in the main memory 21 (step S8 in FIG. 2), and then the data is written on line j (step S9 in FIG. 2).

Thereafter, the memory control circuit 20 sets both the V bit 24 and the M bit 25 of the line j to "1" (step S10 in FIG. 2), and confirms that the data on the cache line i is newer than the data on the main memory 21. Is shown.
As in the case of a read cache miss, the value j of line 27
Normally, is appropriately selected depending on the value of the address Aw and the use status of each line. However, since the method is known, detailed description thereof will be omitted.

FIG. 3 is a diagram showing an operation at the time of data write according to one embodiment of the present invention. With reference to FIG. 3, how the processing at the time of a cache miss is accelerated by the embodiment of the present invention will be described.

FIG. 3 shows the exchange of data between the cache memory 22 and the main memory 21 controlled by the cache memory control method when data is written to consecutive addresses, and the cache operation, similarly to the operation shown in FIG. 5 shows changes in data on the memory 22 and the main memory 21.

In this case, as in FIG.
Assuming that the data size of the line is 16 bytes and the size of the data to be written is 4 bytes, four 4-byte data N0, N1, N
Consider a case where 2 and N3 are written one by one. further,
Similarly to FIG. 7, it is assumed that the data of the address Aw does not exist in the cache memory 22 at the time of the start, and the cache line i that holds the data of the address Aw has the indefinite values U0, U1, U2, and U3. It is assumed to be stored [see 31 in FIG. 3].

First, consider the operation when a request to write the value N0 to the address Aw occurs (see (1) in FIG. 3). At this time, since the data at the address Aw does not exist in the cache, a cache miss occurs. However, in one embodiment of the present invention, unlike the conventional example,
1 line of data M0, M from address Aw on
1, M2, and M3 are not read into the cache line i, and U0 corresponding to the data of 4 bytes from the address Aw in the data of the line i is only overwritten by N0 [FIG. (2) and 32].

Address Aw + of the data on line i
4, data corresponding to Aw + 8 and Aw + 12 are indefinite values U
1, U2, U3 and the values M1, M in the main memory 21
2, M3 is not reflected. However, at the time of the cache hit / miss determination, it is considered that the line i holds 16 bytes of data per line from the address Aw on the main memory 21.

Next, 4-byte data N1 is written to the adjacent address Aw + 4 [see (3) in FIG. 3].
At the time of hit / miss determination, one line 16 from address Aw
Since the data for the byte is treated as existing in the cache memory 22, the write of the data N1 hits the cache, and the data corresponding to the address Aw + 4 on the line i is updated to N1 [see 33 in FIG. 3]. .

Third, 4 is assigned to the adjacent address Aw + 8.
The byte data N2 is written [see (4) in FIG. 3]. At the time of the hit / miss determination, since data of 16 bytes per line from the address Aw is treated as existing in the cache memory 22, the write of the data N2 hits the cache, and the data corresponding to the address Aw + 8 on the line i becomes N2. [See 34 in FIG. 3].

Finally, 4 is added to the adjacent address Aw + 12.
The byte data N3 is written [see (5) in FIG. 3]. At the time of the hit / miss determination, since data of 16 bytes per line from the address Aw is treated as existing in the cache memory 22, this write hits the cache, and the data corresponding to the address Aw + 12 on the line i is updated to N3. [See 35 in FIG. 3].

As described above, all the data on the cache line i has been rewritten by the writing of N0, N1, N2, and N3, and are newer than the data 36 for 16 bytes per line from the address Aw on the main memory 21. Therefore, when data of another address is stored in the line i, it is necessary to first write the data of the line i back to the main memory 21 (see (6) and 37 in FIG. 3).

A comparison between the operation example according to the embodiment of the present invention shown in FIG. 3 and the conventional operation example shown in FIG.
The same result is obtained after writing the value N3 to w. That is, cache line i has values N0, N1,
N2 and N3 [35 in FIG. 3 and 4 in FIG.
6].

However, in the conventional example, reading from the main memory 21 to the cache line i [(17) in FIG. 7] is performed in order to obtain this result. In one embodiment of the present invention, this reading is performed. Did not go. Therefore, in one embodiment of the present invention, the result can be obtained faster than in the conventional example.

Referring to FIG. 3, the reason why it is unnecessary to read data from main memory 21 to a cache line at the time of a cache miss will be described. When data on a certain cache line i is all updated by a plurality of write operations,
Even if data is transferred from the main memory 21 to the cache line i due to a cache miss in which the first write has occurred, the data transferred from the main memory 21 is all overwritten by a plurality of write operations. The final result held by i depends only on the value of the write data, not on the contents of the main memory 21. Therefore, there is no need to read data from the main memory 21 to the cache line.

Generally, there is no guarantee that all data on a certain cache line will be updated by a plurality of write operations. Therefore, the consistency between the contents of the main memory 21 and the contents of the corresponding cache line data must be checked. In order to maintain the contents, it is necessary to read the contents of the main memory 21 to a cache line at the time of a cache miss. However, in a multimedia application or the like, it is often guaranteed that all data on a cache line is updated by a plurality of write operations.

For example, consider expanding a compressed video image by software. Since the decompressed video image is continuously written into a frame buffer of about several hundred kilobytes, all contents of the cache line corresponding to the frame buffer area are updated. Multimedia applications, especially applications that handle video images, often write a large amount of data to the frame buffer, and the elimination of unnecessary read operations has a significant effect of speeding up.

A general write instruction (write, store) according to the conventional cache control method shown in FIG. 6 and a write instruction according to the cache control method according to one embodiment of the present invention shown in FIG. Each of them is prepared as a separate instruction, and the application software programmer uses it properly.

The reason is that it is impossible to determine whether or not all the data on a certain cache line is updated by a plurality of write operations by any hardware mechanism on the general-purpose processor 1. It is also difficult for a high-level language compiler to make the same judgment.

As described above, the general write instruction (write, store) 11 according to the conventional cache control method in the instruction set 10 of the general-purpose processor 1 and the cache according to the cache control method according to the embodiment of the present invention shown in FIG.・
Prepare the write instruction for miss 12 as a separate instruction,
When a cache miss process needs to be performed, the cache line is updated with the write data without reading data from the address of the main memory 21 corresponding to the write address by the cache miss write instruction 12, and the cache line is updated. "1" for both V and M bits
In the case where all data on a certain cache line is to be updated, the read from the main memory 21 to the cache line at the time of a write miss can be omitted to speed up the processing.

Therefore, the time for reading data from the address of the main memory 21 can be reduced. Therefore, it is possible to speed up cache miss processing when writing a large amount of data to consecutive addresses, and improve the execution speed of software including the cache miss processing.

[0084]

As described above, according to the present invention, in a cache memory system including a main memory and a cache memory holding a part of data stored in the main memory, a write cache miss to the cache memory is performed. When an error occurs, the address of the cache memory that stores the data of the write cache is selected, and it is determined whether the data of the cache memory corresponding to the selected address is valid or invalid, and it is determined that the data is invalid. Cache miss processing when writing a large amount of data to consecutive addresses by writing the data at the time of write cache to the selected address without reading the data in the main memory corresponding to the data at times to the cache memory Can be speeded up and its cache miss handling There is an effect that it is possible to improve the execution speed of the software, including.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a cache memory system according to one embodiment of the present invention.

FIG. 2 is a flowchart showing an operation at the time of data writing according to one embodiment of the present invention.

FIG. 3 is a diagram showing an operation at the time of data writing according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a cache memory system according to a conventional example.

FIG. 5 is a flowchart showing an operation at the time of data reading according to a conventional example.

FIG. 6 is a flowchart showing an operation at the time of data writing according to a conventional example.

FIG. 7 is a diagram showing an operation at the time of data writing according to a conventional example.

[Description of Signs] 1 General-purpose processor 2 Memory system 10 Instruction set 11 Write instruction (write, store) 12 Write instruction for cache miss 20 Memory control circuit 21 Main memory 22 Cache memory 23 Tag 24 Valid bit 25 Modify bit 26 Data 27 Cache line

Claims (12)

[Claims] 1. A cache memory system comprising: a main memory; and a cache memory for holding a part of data stored in the main memory, wherein when a write cache miss occurs in the cache memory, the write is performed. Selecting means for selecting an address of the cache memory for storing cache data; determining means for determining whether data in the cache memory corresponding to the address selected by the selecting means is valid or invalid; and Writing means for writing the data at the time of the write cache to the address selected by the selection means without reading the data of the main memory corresponding to the data into the cache memory when the data is determined to be invalid A cache memory system characterized by the above-mentioned. 2. The method according to claim 1, wherein the selecting unit is configured to determine whether the write target address does not match the cache memory address at the time of the data write request, and that the write target address matches the cache memory address even if the write target address matches the cache memory address. 2. The cache memory system according to claim 1, wherein an address for storing the data to be written is selected in any one of cases where the data is invalid. 3. The method according to claim 1, wherein the determining unit determines whether a valid bit indicating whether data in the cache memory corresponding to the address selected by the selecting unit is valid or invalid indicates invalid, and determines whether the address selected by the selecting unit is invalid. Corresponding to the address selected by the selecting means in either of the cases where the modify bit indicating whether the corresponding data in the cache memory is newer than the data in the main memory is not new or not. 3. The cache memory system according to claim 1, wherein data of the cache memory to be executed is determined to be invalid. 4. After the writing means writes the data at the time of the write cache to the address selected by the selection means, a value indicating that the data is valid is set in the valid bit corresponding to the address. 4. The cache memory system according to claim 3, further comprising means for setting a value indicating that said data has been rewritten to said modify bit corresponding to said selected address. 5. A cache control method for a cache memory system including a main memory and a cache memory holding a part of data stored in the main memory, wherein a write cache miss occurs in the cache memory. Selecting the address of the cache memory for storing the data of the write cache, determining whether the data of the cache memory corresponding to the selected address is valid or invalid, and determining that the data is invalid. Writing the data at the time of the write cache to the address selected by the selection means without reading the data of the main memory corresponding to the data into the cache memory when the determination is made. Cache control method. 6. The step of selecting an address of the cache memory includes: when a write request for data does not match an address of the cache memory with the address of the cache memory; 6. The cache control method according to claim 5, wherein an address for storing the data to be written is selected in any one of cases where the data at the address is invalid even if the address is invalid. 7. The step of determining whether the data in the cache memory is valid or invalid is performed when the valid bit indicating whether the data in the cache memory corresponding to the selected address is valid or invalid indicates invalid. The cache memory data corresponding to the address selected by the selection means is newer than the data in the main memory, indicating whether the modify bit is not newer. 7. The cache control method according to claim 5, wherein data of the cache memory corresponding to the selected address is determined to be invalid. 8. After the data at the time of the write cache is written to the address selected by the selecting means, a value indicating that the data is valid is set to the valid bit corresponding to the address, and 8. The cache control method according to claim 7, further comprising the step of setting a value indicating that the data has been rewritten to the modify bit corresponding to the selected address. 9. A recording medium storing a cache control program for causing a computer to control a cache memory that holds a part of data stored in a main memory, wherein the cache control program causes the computer to When a write cache miss occurs in the cache memory, an address of the cache memory for storing the data of the write cache is selected, and it is determined whether the data of the cache memory corresponding to the selected address is valid or invalid. Writing the data at the time of the write cache to the address selected by the selection means without reading the data of the main memory corresponding to the data into the cache memory when the data is determined to be invalid. Characteristic cache control program A recording medium on which a ram is recorded. 10. The cache control program, when causing the computer to select an address of the cache memory, when a write target address does not match an address of the cache memory at the time of a data write request, and 10. The method according to claim 9, further comprising: selecting an address for storing the data to be written in one of the cases where the data of the address is invalid even if the address matches the address of the cache memory. A recording medium on which a cache control program is recorded. 11. The cache control program, when causing the computer to determine whether data in the cache memory is valid or invalid, determines whether data in the cache memory corresponding to the selected address is valid or invalid. When the valid bit indicates invalid, and when the modify bit indicating whether the data in the cache memory corresponding to the address selected by the selecting means is newer than the data in the main memory is not new. The data of the cache memory corresponding to the selected address is determined to be invalid in any one of the above cases.
A recording medium on which the cache control program described above is recorded. 12. The cache control program according to claim 1, wherein after the data at the time of said write cache is written to an address selected by said selection means, said data is valid for said valid bit corresponding to said address. 12. The recording according to claim 11, wherein a value indicating that the data has been rewritten is set in the modify bit corresponding to the selected address. Medium.