JPH03292548A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the deterioration of performance due to the waiting time for a block access required to a main storage at a cache miss by prefetching the block data to a cache from the main storage prior to an original access at a cache miss. CONSTITUTION:When the index results of address arrays 3 and 4 show the cache misses, a block is prefetched to a main storage 10 from a memory access control circuit 9 by an address of a counter 2 after a block is fetched to the storage 10 from the circuit 9 by an address shown in a register 1. That is, an access to be applied to the vicinity of a cache access address from a requester is estimated. Then the probability of existence of data is improved to a cache when the estimated access is carried out. Thus it is possible to prevent the deterioration of performance due to the waiting time for a block access required on the storage 10 at a cache miss.

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a cache memory that stores a copy of a portion of data stored in a main memory in units of blocks. Crossing the fence! Conventionally, in this type of information processing device, fetching of block data into cache memory involves fetching necessary block data serially from main memory only when a cache miss occurs as a result of indexing an address array upon access from a request source. , adopt a method that does not involve pre-emption υ at all, or
Only when there are consecutive accesses from the request source and both consecutive accesses result in a cache miss, the block load data is accessed continuously to the main memory, and the block data is transferred to the main memory for subsequent accesses from the request source. Either a method of pre-fetching from the device is adopted. The conventional block preemption described above requires continuous access from the request source, and if it is not continuous, the access from the preceding request source will result in a cache miss and will be delayed until the block data is fetched from the main memory. This has the drawback that cache miss processing for accesses from subsequent request sources is forced to wait, and data return responses to request sources are delayed, making it difficult to improve performance. j Snake [two

A direct object of the present invention is to provide an information processing device that eliminates performance degradation due to block access wait time to the main storage device required in the event of a cache miss. According to the present invention, there is provided an information processing apparatus having a cache memory that stores a copy of a part of data stored in a main memory in units of blocks, wherein the main memory stores a copy of a part of data stored in the cache memory. a duplicated address array for storing copies of addresses in the cache index, and means for simultaneously indexing the duplicated address arrays using a block address from a cache index request source and a block address subsequent to this block address as index addresses, respectively; There is obtained an information device characterized in that it has means for requesting the main storage device to prefetch a block when the index result is a cache miss. Further, according to the present invention, there is provided an information processing apparatus having a cache memory for storing a copy of a part of data stored in a main memory in units of blocks, wherein an address in the main memory of a block stored in the cache memory is provided. an address array for storing a copy of a cache index; a means for indexing using an index address from a cache index request source; An information processing device is obtained, comprising means for indexing, and means for requesting the main storage device to prefetch a block when the index result is a cache miss. Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In this embodiment, the address register 1 that holds the character access address from the request source and the block address part of this register 1 are added. A counter 2 , a first address array 3 , a second address array 4 , a comparator 5 for detecting a match between the key address field of the address array 3 and the key address field of the register 1 , and a key of the address array 4 A comparator 6 detects a match between the address part and the key address part of the output of counter 2, and the output of fields V and V2 of address arrays 3 and 4 indicates that the results of comparators 5 and 6 are valid. Gates 7 and 8 validate the comparison results, and the outputs of gates 7 and 8 are used as input to determine a cache miss, determine whether or not to pre-fetch a block, and transfer the block data to the main memory 10. The memory access control circuit 9 requests the fetching of the data and controls the change of registered addresses in the cache. In this configuration, the cache access address from the request source is set in the address register 1, and the address array 3 is indexed by the S section (set address section: lower bits of the block address) of this register 1. At the same time, the block address section (K, S section) of register 1 is counted up by +1, a block address one block higher than the requested block is generated by counter 2, and address array 4 is indexed by the set address section. The index result is output as the key address part (Kl, ni 2) of the entry corresponding to comparators 5 and 6, and is outputted as the key address part (Kl, ni 2) of the entry corresponding to comparators 5 and 6, and is output to the comparator 5 and the output of the register 1 part (key part) and the key part of counter 2, respectively. and 6, and address array 3
When the AND result with the registered address valid display output indicated by the vl and V2 fields of 4 is on, each access is determined to be a cache hit, and when it is off, it is determined to be a cache miss. Therefore, when both address array index results are cache hits, the memory access control circuit 9 does nothing, and the data corresponding to the address indicated by register l is requested from the cache data array section not shown in this figure. It will be sent back to its source. Furthermore, when the index result of the address array 3 is a cache hit and the index result of the address array 4 is a cache miss, in addition to the above operation, the memory access control circuit 9 sends a block to the main storage device 10 using the address of the counter 2. A prefetch request is made, and the cache registration address in the address array 4 is changed. Further, when the index result of the address array 3 is a cache miss and the index result of the address array 4 is a cache hit, a block is fetched from the memory access control circuit 9 to the main storage device 10 using the address of the address register 1. The data corresponding to the address indicated in register 1 is returned from the data registration section to the cache data array section from the main storage device 10 to the request source, and the change of the cache registration address in the address array 3 is performed by the memory access control circuit 9. This is done by Furthermore, when the index results of both address arrays 3 and 4 are both cache misses, the block fetch from the memory access control circuit 9 to the main storage device 10 at the address indicated by the register is performed, and then the address of the counter 2 is Then, the memory access control circuit 9 preempts the block from the main storage device 10. That is, it predicts an access from a request source to a location near a cache access address, and increases the probability that data will exist in the cache when this access occurs. FIG. 2 is a block diagram showing another embodiment of the present invention,
Parts that are equivalent to those in Figure 1 are indicated by the same symbols ◇ Parts that are different from Figure 1 are two address registers (11 and 12) that hold cache access addresses from request sources.
), the address register 11 holds the cache access address from the current request source, and the address register 12 holds the subsequent cache preemption access address. The contents of these registers 11 and 12 are used to index each address array 3 and 4, respectively. In such a configuration, the first address of the cache access from the request source is set in the register 11, and the second address is set in the register 12, and the address array 3 is indexed by the 81st part of the register 11, and at the same time, the 82nd address of the register 12 is set.
The address array 4 is indexed in the section. The index result is output as the key address part (Kl, 2) of the entry corresponding to comparators 5 and 6, and is compared with the output of each key part of registers 11 and 12 in comparators 5 and 6, respectively. V and v of address arrays 3 and 4
When the AND result with the registered address valid display output shown in field 2 is on, each access is determined to be a cache hit, and when it is off, it is determined to be a cache miss. The subsequent operation is the same as that of the embodiment shown in FIG. FIG. 3 is a block diagram showing another embodiment of the invention. This embodiment includes an address register 41 that holds a cache access address from a request source, a counter 42 that adds up the block address part of this register 41, an address array 43, and a cache access address that is output from the register 41. There is still a selector 44 that selects whether to output the output of the counter 42, a comparator 45 that detects a match between the key address part of the address array 43, and the key address part of the selector 44, and the result of the comparator 45 is valid. A gate 46 validates the comparison result with the output of field V of the address array 43 indicating that there is a cache miss, and a cache miss is determined using the output of the gate 46 as input, and it is determined whether or not to prefetch the block. It is comprised of a memory access control circuit 47 that requests fetching of block data to the storage device 48 and controls changes to registered addresses in the cache. In this configuration, the cache access address from the request source is set in the register 41, the output of the register 41 is first selected by the selector 44, and the address array 43 is indexed by eight portions of the selector output. The index result is output as the key address part (K) of the entry corresponding to the comparator 45, and the key part output of the selector 44 and the comparator 45
When the AND result with the registered address valid display output indicated by the V field of the address array 43 is on, it is determined to be a cache hit, and when it is off, it is determined to be a cache miss. Subsequently, the block address portion of the output of the cache access address register 41 from the request source is counted by +1, and the counter 42 generates a block address 91 places higher than the requested block. The address is selected by the selector 44 and the selector 44
The address array 43 is indexed in the 0 set address section,
Through processing similar to the above comparison, a hit/miss result is obtained at the output of the AND gate 46. Continuous indexing of these address arrays 43 is controlled by a memory access control circuit 47, and is performed serially under selection control of the selector 44 from the control circuit 47. Except for the fact that the address array 43 is indexed serially, subsequent block access from the memory access control circuit 47 to the main storage device 48 and change of the cache registration address to the address array 43 are performed in accordance with the embodiment shown in FIG. is the same as FIG. 4 is a block diagram showing still another embodiment of the invention. This embodiment includes an address register 41 that holds a cache access address from a request source, a next data fetch flag (NDF) 62 that indicates that there is a cache access following the address of register 4, and a block of registers 41. Counter 42 that adds up the address part
, a selector 44 that selects whether to output the cache access address as the output of the register 41 or the counter 42, a counter 65 that adds the intra-block address part of the register 41 to the next data address, and a When a carry occurs and the NDF 62 is on, there is a gate 66 that instructs block prefetch, and a block prefetch instruction FF (NB) that holds the output of gate 66 and instructs the counter 42 to select the selector 44 output.
R) 67, the address array 43 indexed by the selector 44, the comparator 45 that detects a match between the key address part of the address array 43 and the key address part of the selector 44, and the result of the comparator 45 is valid. A gate 46 validates the comparison result based on the output of the field ■ of the address array 43 indicating a cache miss, and a cache miss is determined using the output of the gate 46 as input, and it is determined whether or not to prefetch the block. It is composed of a memory access control circuit 47 that requests fetching of block data to the device 48 and controls changes to registered addresses in the cache. In this configuration, the cache access address from the request source is set in the register 41, and the next data fetch flag is set in the NDF 62. First, the output of the register 41 is selected by the selector 42, and 8 parts of this selected output are used to select the address array 43. indexed. The index result is output as the key address part (K) of the corresponding entry to the comparator 45, and is compared with the key part output of the selector 44 in the comparator 45, and is outputted to the address array 43.
When the AND result with the registered address valid display output indicated by the V field is on, it is determined that there is a cache hit, and when it is off, it is determined that there is a cache miss. During indexing of the address array 43, the block address part (B part) of the register 41 is counted +1 by the counter 65 and updated to the next data address, and when there is a carry from the counter 65, that is, when the block address part changes. In this case, the next block preemption instruction FF NBR67 is set via the gate 66 under the condition that the NDF 62 is on. When the NBR 67 is turned on, the next block address whose address in the register 41 is incremented by 1 by the counter 42 is selected by the selector 44, the address array 43 is indexed following the cache access address from the request source, and the same process as above is performed. The result of the hit/miss is obtained at the output of the AND gate 46. When the NBR 67 is off, that is, when the next data fetch does not exceed a block, or when the next data fetch is unnecessary, the above processing is not performed. Continuous indexing of these address arrays 43 is controlled by a memory access control circuit 47, and is performed serially under selection control of the selector 44 from the control circuit 47. The subsequent block access from the control circuit 47 to the main memory 48 and the change of the cache registration address in the address array 43 are the same as in the embodiment shown in FIG. 1, except that the address array 43 is indexed serially. It is. j = 11 As explained above, according to the present invention, the presence or absence of the block in the cache is determined in advance by accessing the block following the actually accessed block address or the block required for the next access. By detecting a cache miss and pre-fetching block data from the main memory to the cache prior to the original access, it reduces performance degradation due to the waiting time required to access a block to the main memory when a cache miss occurs. There is an effect that it can be done.

[Brief explanation of the drawing]

1 to 4 are block diagrams of each embodiment of the present invention. Explanation of symbols of main parts 1, 11.12.41...Address register 3.4.
43...Address array 5.6.45...Comparator 9.47...Memory access control circuit 10.48...
・Main storage device Figure 1

Claims (2)

[Claims] (1) An information processing device having a cache memory that stores a copy of a part of data stored in a main memory in units of blocks, which stores a copy of the address in the main memory of the block stored in the cache memory. means for simultaneously indexing the duplicated address arrays using a block address from a cache index request source and a block address subsequent to this block address as index addresses, respectively; An information processing apparatus comprising: means for requesting the main storage device to prefetch a block when . (2) An information processing device having a cache memory that stores a copy of a part of data stored in a main memory in units of blocks, which stores a copy of the address in the main memory of the block stored in the cache memory. means for indexing using an index address from a cache index request source; and means for continuing to index the address array using a block specified address consecutive to the index address as an index address when the index result is a cache miss. , and means for requesting the main storage device to prefetch a block when the index result is a cache miss.