JPS57135498A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS57135498A
JPS57135498A JP2108181A JP2108181A JPS57135498A JP S57135498 A JPS57135498 A JP S57135498A JP 2108181 A JP2108181 A JP 2108181A JP 2108181 A JP2108181 A JP 2108181A JP S57135498 A JPS57135498 A JP S57135498A
Authority
JP
Japan
Prior art keywords
writing
memory
memory cell
output
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2108181A
Other languages
Japanese (ja)
Other versions
JPS618518B2 (en
Inventor
Hiroki Kamata
Masahiro Shoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2108181A priority Critical patent/JPS57135498A/en
Publication of JPS57135498A publication Critical patent/JPS57135498A/en
Publication of JPS618518B2 publication Critical patent/JPS618518B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Read Only Memory (AREA)

Abstract

PURPOSE:To know the frequency of writing performed at some point in time by writing data in additional memory cells other than those characteristic to a memory and by inputting a pulse to a special terminal. CONSTITUTION:A memory with (m+1) input terminals is divided into two blocks of input buffers, and the outputs of the buffer blocks are inputted to two decoders Decy3 and Decx4. During memory writing, a terminal OE is held at an H to close an output buffer 7, and a higher voltage than in reading is applied to a writing-voltage terminal to write data in corresponding bits of specified addresses through input buffers 7' and 3. When a memory cell 5 or a memory cell part 12 for writing-frequency storage enters into reading operation, a sense amplifier 6 amplifies the output of a corresponding memory cell and it is read to output terminals O0-O7 through an output buffer 7.
JP2108181A 1981-02-16 1981-02-16 Semiconductor memory Granted JPS57135498A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2108181A JPS57135498A (en) 1981-02-16 1981-02-16 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2108181A JPS57135498A (en) 1981-02-16 1981-02-16 Semiconductor memory

Publications (2)

Publication Number Publication Date
JPS57135498A true JPS57135498A (en) 1982-08-21
JPS618518B2 JPS618518B2 (en) 1986-03-14

Family

ID=12044927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2108181A Granted JPS57135498A (en) 1981-02-16 1981-02-16 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS57135498A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58215795A (en) * 1982-06-08 1983-12-15 Toshiba Corp Non-volatile memory device
JPS59162695A (en) * 1983-03-07 1984-09-13 Nec Corp Storage device
JPS6196598A (en) * 1984-10-17 1986-05-15 Fuji Electric Co Ltd Count data memory method of electric erasable p-rom

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58215795A (en) * 1982-06-08 1983-12-15 Toshiba Corp Non-volatile memory device
JPS59162695A (en) * 1983-03-07 1984-09-13 Nec Corp Storage device
JPS6196598A (en) * 1984-10-17 1986-05-15 Fuji Electric Co Ltd Count data memory method of electric erasable p-rom

Also Published As

Publication number Publication date
JPS618518B2 (en) 1986-03-14

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