JPS56143071A - Bus coupling system - Google Patents

Bus coupling system

Info

Publication number
JPS56143071A
JPS56143071A JP4667180A JP4667180A JPS56143071A JP S56143071 A JPS56143071 A JP S56143071A JP 4667180 A JP4667180 A JP 4667180A JP 4667180 A JP4667180 A JP 4667180A JP S56143071 A JPS56143071 A JP S56143071A
Authority
JP
Japan
Prior art keywords
memory
data
bus
circuit
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4667180A
Other languages
Japanese (ja)
Other versions
JPS6342303B2 (en
Inventor
Kenji Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4667180A priority Critical patent/JPS56143071A/en
Publication of JPS56143071A publication Critical patent/JPS56143071A/en
Publication of JPS6342303B2 publication Critical patent/JPS6342303B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To reduce access to a main memory, by providing a bus coupler with a circuit monitoring whether the memory write request is successful or not and a circuit which rewrites the former data in memory with written-in data. CONSTITUTION:A plurality of processors PCs 1 are coupled with the main memory 5 via the bus coupler and bus 7 respectively. When the memory write-in request from PC1 to the memory 5 is produced on the bus 7, the montor circuit 21 judges if the data to the address is stored in the memory 30 in the bus coupler. If stored, the replacement circuit receives the instruction to fetch the data. When the data is fetched and a signal that the write-in to the main memory 5 is successuful on the bus 7 is generated, the circuit 22 replaces the data in the memory 30 with new data. Thus, the change of the data of the memory 5 is effected on the memory in the bus coupler, the number of times of access is reduced and the system performance is increased.
JP4667180A 1980-04-09 1980-04-09 Bus coupling system Granted JPS56143071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4667180A JPS56143071A (en) 1980-04-09 1980-04-09 Bus coupling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4667180A JPS56143071A (en) 1980-04-09 1980-04-09 Bus coupling system

Publications (2)

Publication Number Publication Date
JPS56143071A true JPS56143071A (en) 1981-11-07
JPS6342303B2 JPS6342303B2 (en) 1988-08-23

Family

ID=12753816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4667180A Granted JPS56143071A (en) 1980-04-09 1980-04-09 Bus coupling system

Country Status (1)

Country Link
JP (1) JPS56143071A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5173852A (en) * 1974-12-23 1976-06-26 Fujitsu Ltd Batsufua memoriojusurudeetashorishisutemu

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5173852A (en) * 1974-12-23 1976-06-26 Fujitsu Ltd Batsufua memoriojusurudeetashorishisutemu

Also Published As

Publication number Publication date
JPS6342303B2 (en) 1988-08-23

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