JPS6342303B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus coupling system in a multiprocessor system having a multibus configuration.

A disadvantage of a multiprocessor system with a multibus configuration is that when the main memory shared by each processor is frequently accessed, the performance of the system is significantly degraded due to bus or memory contention. According to one experimental example, in a multiprocessor system with 10 processors, the percentage of main memory usage or bus occupancy is 1/1 when there is no interference from other processors. 3
If a certain program is given to each processor for execution, the throughput is only a little more than three times that of a single processor system.

For this purpose, in a multiprocessor system with a multibus configuration, a local memory is provided for each processor. This is intended to reduce the frequency of access to main memory by implementing frequently used data and programs in local memory, but in reality it is difficult to find an efficient distribution method. It has not been put to practical use because it is difficult.

The purpose of the present invention is to overcome the drawbacks of the prior art.
It is an object of the present invention to provide a bus-coupled system that reduces access to main memory solely by hardware functions without the aid of software.

According to the bus coupling system of the present invention, for data stored in the memory in the bus coupling device, a memory write request is generated on the other bus and monitors whether or not the request is successful. A bus coupling system is obtained in which the bus coupling device is provided with an updater consisting of a replacement circuit that takes in data and, if successful, replaces the previous data in the memory in the bus coupling device with the written data. .

Next, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the bus coupling system of the present invention.

Data is read from the main memory as follows. Processors 1 and 2 request data by sending required addresses to bus coupling devices 3 and 4. If this data is stored in the bus coupling devices 3, 4, the requested data is returned from the bus coupling devices 3, 4 to the processors 1, 2. If this data is not stored in the bus coupling device 3, 4, the bus coupling device 3, 4 stores the requested memory address in order to ensure that subsequent memory accesses are subsequently made from the bus coupling device. A request is made to the main memory 5 for a data group of consecutive addresses including multiple rotations. Then, the bus coupling devices 3 and 4 write the data group sent from the main memory 5 into a certain area of their own memory, and send out the required data to the processors 1 and 2.

Data is written to the main memory 5 as follows. Addresses and data generated by processors 1 and 2 pass through bus coupling devices 3 and 4 and are sent to main memory 5. However, at this time, each bus coupling device 3 connected to the main memory 5,
4, if the data corresponding to the required address being accessed is stored in its own memory, the data is taken in once. If the writing of data to the main memory is successful, it rewrites its own data with new data.

The associator 10 will be explained in detail using FIG. In FIG. 2, processor 1 sends a memory read command to main memory 5. In FIG.
This command is sent to the determination circuit 11 via the bus 6. The determination circuit 11 determines whether the required data is stored in the memory 30. If the required data is available, the data is requested from the readout circuit 12. If the required data is not present, the write circuit 13 is requested to read the required data from the main memory 5.

The read circuit 12, which is requested to read data from the memory 30, reads the address of the required data from the memory 3.
0, data is obtained from the memory 30 and returned to the determination circuit 11.

The write circuit 13 requested to read data from the main memory 5 requests the main memory 5 via the bus 7 for a data group of a plurality of consecutive addresses including the requested memory address.
The write circuit 13 sends the data group returned from the main memory 5 to the memory 30 and requests its writing, and returns the required data to the determination circuit 11.

Upon receiving the required data, the determination circuit 11 sends the data to the processor 1 via the bus 6.

The determination circuit 11 includes an address storage section that stores the address on the main memory of the data stored in the memory 30, and a circuit that matches the address sent from the processor 1 with the address stored in the address storage section. a comparison unit that compares whether or not there is a corresponding one, and a readout circuit 12 that reads data from the memory 30 if there is a corresponding one as a result of the comparison.
and a sending unit for sending data from the read circuit 12 or the write circuit 13 to the bus 6. If there is no matching data as a result of comparison, the data is sent to the write circuit 13. a request unit that requests the transfer of a data group from the main memory 5 to the memory 30, and a registration unit that registers the address of the data group stored in the memory 30 as received from the write circuit 13 in the address storage unit. and performs the above operations.

The write circuit 13 includes a reception section that receives a request from the determination circuit 11, a request section that requests a data group of a plurality of consecutive addresses including the requested memory address from the main memory 5, and a request section that receives the read data. a writing section that writes the group to the memory 30, and a judgment circuit 1 that processes the data requested from the processor 1.
1, and performs the above operations.

A detailed explanation of the updater 20 will be given using FIG. 3. In FIG. 3, it is assumed that a memory write request to the main memory 5 occurs on the bus 7. At this time,
The monitoring circuit 21 determines whether data for that address is stored in the memory 30.
If so, the replacement circuit 22 is instructed to take in that data. Replacement circuit 2
2, when data is captured and a signal indicating that writing to the main memory has been successfully generated is generated on the bus.
Replace the data in the memory 30 with new data.

The monitoring circuit 21 includes a comparison section that compares whether or not an address on the bus 7 at the time of main memory writing matches an address stored in the address storage section of the determination circuit 11, and there is a matching section. At the time, the request section requests the replacement circuit 22 to replace the data with the data on the bus, and performs the above operation.

The replacement circuit 22 includes an acquisition section that takes in data on the bus 7 when requested by the monitoring circuit 21;
Consists of a monitoring section that monitors whether writing to the main memory on the bus 7 is successful or not, and a replacement section that replaces old data in the memory 30 with new data imported by the importing section when success is detected by the monitoring section. is,
Perform the above operation.

The memory 30 will be explained in detail using FIG. 4. In FIG. 4, it is assumed that a data group is sent from the associator 10 to the memory circuit 30. At this time, the selection circuit 31 checks whether there are any unused memory cells in the memory circuit 33, and if so, selects one of them. If there is no such thing then FIFO
The circuit 32 is asked to make a selection. FIFO requested
The circuit 32 selects the memory cells that have been written to the oldest. Once a memory cell is selected, memory circuit 33 writes a group of data into that memory cell.

The selection circuit 31 includes a storage section that indicates whether each memory cell is used or not, a determination section that indicates whether or not there is a memory cell that can be used from an explicit section, and a determination section that indicates whether or not there is a memory cell that can be used. A selection section that selects the memory cell and puts the currently selected memory cell into use, and a FIFO circuit 32 that forcibly selects a memory cell when there is no usable memory cell.
The system is comprised of a requesting section that makes requests to perform the above-mentioned operations.

As described above, the bus-coupled system of the present invention extends changes to data on the main memory to data in the bus-coupled system, thereby reducing the number of accesses to the main memory and contributing to improved system performance. do.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of the bus coupling system, FIG. 2 is a block diagram of the associator, FIG. 3 is a block diagram of the updater, and FIG. 4 is a block diagram of the memory. In the figure 1, 2... Processor, 3, 4... Bus coupling device, 5... Main memory, 6, 7... Bus, 10
. . . associator, 20 . . . updater, 30 . . . memory.

Claims (1)

[Claims] 1. In a bus coupling device in a multiprocessor system with a multi-bus configuration, a memory write request occurs on the bus to which the main memory is coupled for data stored in the memory in the bus coupling device. An updater consisting of a monitoring circuit that monitors whether or not the data has been successfully written, and a replacement circuit that takes in the written data and, if successful, replaces the previous data in the memory in the bus coupling device with the written data. A bus coupling system characterized by comprising: