JPH0750466B2 - Parallel computer cache memory control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A parallel computer cache memory control system in a parallel computer in which a cell having a processor is connected to other cells via a communication port and data is distributed and held by each cell, The data required for at least the own cell corresponding to each cell for the purpose of reducing the overhead for interprocessor communication and the overhead for data relay in the data access to the cell. , And, if necessary, for data transferred via its own cell, a cache memory holding the data is provided, and the data access request from a certain cell is desired on the cache memory in the passing cell. If there is any data that does not exist, the data is sent to the source of the data access request. Configured to forward to

[Industrial application field]

The present invention relates to a parallel computer cache memory control method, and more particularly, to a parallel computer cache memory control in a parallel computer in which a cell having a processor is connected to another cell via a communication port and data is distributed and held in each cell. Regarding the scheme.

With the development of semiconductor technology, it has become possible to realize high-performance computers in a compact size.
0-scale parallel computers are being considered. In such a parallel computer, it is inevitable that individual cells hold data in a distributed manner, but the overhead for communication between processors and the overhead for data relay pose a problem.

[Conventional technology]

As a method of storing common data in a parallel computer,
Data is distributed in individual cells and required data is accessed through interprocessor communication.

In this case, the message in the inter-processor communication includes a data access request and data transferred in response to the request. Each cell has at least a data placement table that indicates on which cell the requested data resides and a data direction table that indicates the shortest path for communicating with a cell. It has a function to issue data access requests and a function to relay data.

FIG. 3 shows an example of a cell structure according to the conventional method. cell
A local bus 12 and a communication bus 13 are present in 2-i. The processor 10 and the main memory 11 are connected to the local bus 12. Further, the communication bus 13 is connected to a plurality of transmission ports 22-i and a plurality of reception ports 23-i.

A communication control unit 24 exists between both buses 12 and 13, and the communication control unit 24 includes a DMA controller (DMAC) 14, an address register (AR) 15, and a request register (RR) 1.
6, request multiplexer (REQ MPX) 17, request controller (REQCTL) 18, request demultiplexer (REQDMPX) 19, address conversion circuit (Rdid → ME
M) 20, Micro sequencer that controls the entire communication control unit
There are 21. The data arrangement table and the data direction table referred to in the present invention are, for example, the main memory 11
Think of it as held on.

The data stored in a distributed manner is stored in the main memory 11 on a plurality of cells 2-i. For example, a data id (hereinafter referred to as “did” in the meaning of data id) is attached to each storage unit of 4 KB. Is managed. Needless to say, did
Indicates data uniquely across all cells.

An address starting from "1" (hereinafter referred to as pid in the meaning of port id) is attached to each of the transmission port 22-i and the reception port 23-i.

When the own cell makes a data address request, the above pid is set to pid = in the request register (RR) 16.
0, and the data access request source (the own cell id, that is, the cid meaning the cell id is its own) and the destination of the data access request (the above cid is given as "0" or N ---) If the desired data exists in the main memory 11 on its own cell, the above "0"
Give) and give.

In communication between cells, the requested did is transferred in the case of a data access request, and the did and the data of the data are transferred in the case of data, and both can be distinguished and identified at each port. it can.

When the processor 10 makes a data access request, the processor 10 sets the request register (RR) 16 as described above and sets the storage destination of the requested data in the address register (AR) 15. The data access request from another cell and the data access request from the self-processor 10 are the request did and the request pid for the pair of the did and the pid.
Is queued in the request multiplexer (REQ MPX) 17 as a pair of Rdid and Rpid that means 1
Request controller (REQCTL) taken out one by one
Guided to 18.

The request controller (REQCTL) 18 is Rd above.
When the id / Rpid pair is received, the following processing is performed. That is, (1) The cell of the cell holding the desired data by referring to the above-mentioned data arrangement table using the above Rdid as a key
Find the id (cid).

(2) The above-mentioned data direction table is referenced with the above cid as a key, and the port id (Opid) corresponding to the cell having the desired data is obtained.

(3) If Opid = 0 (in this case, it means that the self cell has the required or desired data), (i) Address conversion circuit Rdid → MEM) 20 is used.
If the address is converted from Rdid to its own main memory 11 and (ii) Rpid = 0 (in this case, it is the self cell that issued the request), the above address conversion circuit Start the DMA controller 14 so that the contents in the main memory 11 at the address obtained in 20 are transferred to the address in the main memory 11 designated by the address register (AR) 15, and (iii) Rpid If ≠ 0 (in this case, it means that another cell has issued a request), the contents on the main memory 11 at the address obtained by the address conversion circuit 20 are transferred to the port designated by the Rpid. The DMA controller 14 is activated so as to transfer the data.

(4) If Opid ≠ 0 (in this case, the own cell does not have the data), Rd from the port indicated by the relevant Opid
Send the data access request corresponding to id.

When data is received, the following processing is performed. That is, (5) the did of the received data is compared with the content of the request register (RR) 16. If they are the same, it is the data requested by the own cell, and the DMA controller 14 is activated so that the data is transferred from the receiving port to the address on the main memory 11 indicated by the address register (AR) 15.

(6) If they are not the same, this data corresponds to a reply of a request from another cell previously, so DMA is performed so that data is transferred from the receiving port to the desired transmitting port. Start the controller 14.

[Problems to be solved by the invention]

In the case of the conventional method described with reference to FIG. 3 above, as one cell accesses data existing in another cell as the number of cells increases to several hundreds to several thousands, inter-cell communication is performed. The average number of times communication is performed increases, and the overhead becomes undesirably large.

An object of the present invention is to reduce the overhead for communication between processors and the overhead for data relay in the data accelerator performed for other cells.

[Means for solving problems]

FIG. 1 shows the principle configuration of the present invention. In the figure, reference numeral 1 is a host computer, 2-i is a cell, 3-i is a data arrangement table which stores information for identifying the cell holding the data indicated by did, 4-i Is a data direction table which stores information indicating the shortest path for communicating with a cell, and 5-i represents a cache memory prepared in the present invention. Reference numeral 6 is a command bus for communicating commands between the host computer and each cell, and 7 is a communication bus between each cell.

The cache memory 5-i for each cell 2-i contains
For example, (i) data recently used by self-cell 2-i, (i
i) Regarding the data corresponding to the data access request made by the other cell 2-j, the data when the data passes through the self cell 2-i is held.

Needless to say, each cell 2-i includes a processor 10 and a main unit in the case of the conventional method described with reference to FIG.
It has a memory 11, a communication control unit 24, a transmission port 22-i, a reception port 23-i, and the like.

[Action]

Data access is performed as follows. That is, (1) It is assumed that the program of cell 2-1 now needs some data.

(2) Cell 2-1 refers to the data arrangement table 3-1 and
Know that the desired data resides in cells 2-12, for example.

(3) If the desired data exists in its own cache memory 5-1, the data is returned to the program and the process ends.

(4) If it does not exist in its own cache memory 5-1, cell 2-1 uses data direction table 4-1 to send a data access request to cell 2-12. Referring to the drawing, it is known that the direction of the cell 2-2 or the cell 2-5 is good. And, in the present case, it is assumed that cell 2-2 is selected.

(5) Cell 2-1 sends a data access request to cell 2-2 and waits for data to be sent.

(6) Upon receiving the data access request, the cell 2-2 checks whether the data is in its own cache memory 5-2.

(7) If it is in the cache memory 5-2, the data is returned to the cell 2-1 to finish.

(8) Cell 2-12 if not in cache memory 5-2
The data direction table 4-2 is checked in order to send the data access request to the cell, and the data access request is issued to, for example, the cell 2-3, and the process ends.

(9) Hereafter, the cell 2-3, the cell 2-4, and the cell 2-8 perform the same processing as in the case of the cell 2-2, and the data access request is issued to the cell.
It reaches 2-12.

(10) When the cell 2-12 learns that its own data has been requested, it reads the desired data from the main memory 11 and sends the data in the direction of the data access request.

(11) When the cell 2-8 receives the data for the cell 2-1 from the cell 2-12, it registers the data in its own cache memory 5-8. If cache memory 5-8 is full, discard the oldest or least recently used data and register new data.

(12) Further, the cell 2-8 returns the data in the direction of the cell 2-4 on the side where the data access request is made.

(13) After that, the cells 2-4, 2-3, and 2-2 perform the same processing as in the case of the cell 2-8, and the data is sent to the cell 2-1.

(14) The cell 2-1 registers the received data in the cache memory 5-1 and passes it to the program.

As described above, since the transfer of the data access request and the transfer of the corresponding data are performed,
If the desired data exists in the cache memory of its own cell or in the cache memory of the cell through which the data access request passes, the data
The distance for access is small.

In the above description, the case where a certain cell reads data has been described. Of course, the same process cannot be performed when writing data, but the process of rewriting or invalidating a part of the data in the cache memory in each cell through which the data access request passes is not possible. ， It is not always easy. However,
For example, when handling CAD data or image data with a parallel computer, the frequency of reading is extremely high compared to the writing of data, and only certain cells use certain cells. The frequency is high. For this,
The processing described with reference to FIG. 1 above is also sufficiently useful. Of course, there is a well-known means such as a broadcast process for properly performing the cache coherency operation necessary for rewriting data, which requires a long processing time and a high cost process.
It's not impossible.

〔Example〕

FIG. 2 shows an embodiment of a cell in the case of the present invention.
Reference numerals 10 to 24 in the figure correspond to FIG. 3, 5-i-1 represents a data storage section in the cache memory, and 5-i-2 represents a tag storage section in the cache memory.

The data access request is processed as follows.

(1) The data arrangement table 3-i is referenced with Rdid as a key to obtain cid.

(2) The data direction table 4-i is referenced with the cid as a key, and the opid is obtained.

(3) If Opid = 0, (i) the address conversion circuit 20 is used to convert the Rdid to an address for its own main memory 11, and (ii) if Rpid = 0, the address conversion circuit 20 Main memory at the address obtained in 11
Start the DMA controller 14 so that the above contents are transferred to the address in the main memory 11 designated by the address register (AR) 15. If (iii) Rpid ≠ 0, the address conversion circuit 20 Main memory at the obtained address
11. The DMA controller 14 is activated so that the above contents are transferred to the port indicated by the Rpid.

(4) If Opid ≠ 0, (i) Rdid is used as a key to refer to the tag storage unit 5-i-2 in the cache memory, and (i
i) On hit, activate the DMA controller 14 so that the data from the data storage unit 5-i-1 in the cache memory is transferred to the desired port, and (iii) If no hit, enter the desired port Sends a data access request corresponding to Rdid.

When data is received, the following processing is performed. That is, (5) the did of the received data is compared with the content of the request register (RR) 16. If they are the same, it is the data requested by the own cell, and the DMA controller 14 is activated so that the data is transferred from the receiving port to the address on the main memory 11 indicated by the address register (AR) 15.

(6) If they are not the same, this data corresponds to a reply from a request from another cell previously, so the DMA controller 14 should perform data transfer from the receiving port to the desired transmitting port. To start.

(7) Register the received data in the cache memory 5-i. If it is full, delete other data and register. The algorithm for this deletion is
Known LRU, FIFO, random method, etc. can be used.

〔The invention's effect〕

As described above, according to the present invention, it is possible to improve the processing speed in accessing the data held in a distributed manner, particularly regarding the data reading.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is an embodiment of a cell in the case of the present invention, and FIG. In the figure, reference numeral 1 is a host computer, 2-i is a cell, 3-i is a data allocation table, 4-i is a data direction table, 5-i is a cache memory, 10 is a processor, 11 is main memory, and 22. -i is a transmission port, 23-i is a reception port, and 24 is a communication control unit.

Claims (1)

[Claims] 1. A processor (10) and a main memory (11)
And a cell (2-i) having at least two or more communication ports (22,23) connected to another cell (2-j) via the communication port (22,23) in parallel. In the computer, for each individual cell (2-i), the data arrangement table (3-i) that indicates which cell (2) the individual data exists on, and to communicate with a certain cell A data direction table (4-i) that stores information that indicates a preferred route for storing the data, and a cache memory (5--) that holds the data required by at least its own cell (2-i).
i) and, when one cell (2-i) accesses the desired data, the cell (2-k) through which the data access request to access the data passes If the desired data exists in the cache memory (5-k) on the 2-k), the existing data is transferred to the cell (2-) that issued the data access request.
The parallel computer cache memory control method is characterized in that it is transferred to i).