JPH0247739A - Control system for main storage device - Google Patents

Abstract

PURPOSE:To increase the data transfer speed by providing a buffer (M2) where only write request information (W) of the output of a buffer (M1) where read request information (R) and information (W) are stored is stored and preferentially sending information W in the case of coincidence between addresses of buffers M1 and M2 but preferentially sending information R in the other cases. CONSTITUTION:A request buffer 7 outputs various information 2, 3, and 4 in the acceptance order. A detecting circuit 9 detects write request information W from them and fetches the address 2, data 3, and information W into a store buffer 11 separatedly from one another. When the store buffer is filled up, a request buffer 7 stops the output with respect to information W but outputs read request information R to a priority level discriminating circuit 12. This circuit 12 preferentially sends information W when addresses of the output R of the request buffer 7 and the output W of the store buffer 11 coincide with each other, but otherwise, the circuit 12 preferentially sends information R.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a control method for a main storage device in a Kameko computer system.

[Conventional technology]

FIG. 2 shows a block diagram of a conventional main memory control circuit in an electronic computer system.

l is the address given to main memory B, data, Read
Or a sprint-style pass line on which control information such as Write is carried, 2 is address information in pass line 1,
3 is data information, 4 is read R for main memory B
or write W information, 5 is an address judgment circuit that judges whether it is a request to its own main storage device B, 6 is the judgment result information, and 7 is a FIFO structure that stores various information 2.3.4 according to the judgment result information 6. A request buffer 8 is a memory controller that controls the main storage device B according to requests from the request buffer 7. Pass line 1 has cpuA
is connected, and CPU A accesses main memory B through this control circuit by issuing various request information. The address range within the main memory device B is registered in the address determination circuit 5 in advance.

Next, the operation will be explained. The address determination circuit 5 determines whether the information request (R/W) transmitted to the path line 1 is an address accepted by its own main storage device B. The request buffer 7 receives the judgment result information 6, and when the judgment result is true, it sends various information 2 from the path line 1.
, 3.4 respectively. The request buffer 7 has several stages of buffers and has a FIFO structure, and takes in various pieces of information 2, 3, and 4 until the internal buffer is full. When the request buffer 7 becomes full, information rAf that the request buffer 7 is full is transmitted to the path line 1. Request for various information (R
/W) After receiving the information r, cpuA that issues the request (R/W) does not issue any subsequent requests (R/W) until there is space in the request buffer 7. On the other hand, when the request buffer 7 receives a request (R/W), it stores it in its own buffer. At this time, in the case of write request W, the data to be written is also stored in the buffer, so the request buffer 7 becomes full quickly.
Information f is output.

Next, the request buffer 7 issues the loaded various information 2.3.4 to the memory control circuit 8 in order from the oldest request (R/W). request buffer 7
waits for the processing of the memory control circuit 8 to be completed, and as soon as the processing of the memory control circuit 8 is completed, the next request (R
/W) is issued to the memory control circuit 8.

The memory control circuit 8 receives request contents (read request R1 or write request W) from the request buffer 7.
), the read R1 or write W operation for the address information 2 to the main memory device B is performed. The above process continues until the request buffer 7 is empty, that is, the main memory B
This process is repeated until there are no requests (R/W) for the data.

[Problem to be solved by the invention]

The conventional main memory control circuit is configured as described above, so when there are many write requests W, the request buffer 7 quickly becomes full and requests (R/W) are not issued to the CPUA. The tendency for the stop information f to be output increases. Therefore, there is a drawback that even when CPUA attempts to read data from main memory B, it is forced to wait for a long time.

This invention was made in order to solve the above-mentioned problem, and the read request R to the main storage device is not related to the previous write request W, and the read request R is
It is an object of the present invention to provide a control method for a main memory device that allows data to be accepted as quickly as possible and speeds up data transfer to a requesting CPU side.

[Means to solve the problem]

In this invention, request information 4 is accepted in a main memory control method in which central processing unit A accesses main memory B with read R and write W request information 4 including designated addresses 2 and 2'. is provided with a first buffer 7 for temporary storage in order, and this first buffer 7
The reception starts with the write W of the request information 4 that is output in order.
A second buffer 11 is provided which temporarily stores only the request information 4 in order, and requests 1 output from the first buffer 7 are provided.
If the address 2 of 179H4 matches the address 2' of the write W request information 4 output from the second buffer 11, the write W request information 4 is sent to the main storage device B with priority, and the other always the first buffer 7
The read R request information 4 outputted from the main storage device B is given priority and sent to the main storage device B.

[Operation 5] In the control method of the main memory device according to the present invention, the write W request information 4 is separated from the requests output from the first buffer 7 and is temporarily fetched into the second buffer 11.
The main storage device B is accessed by taking out the read R request 4 from the buffer 7 with priority. When there are no more read R requests, the write W request information 4 is taken out from the second buffer 11 and written to the main storage device B. When address 2 of read R request information and address 2' of write W request information are equal, priority is given to the write W request, and after writing the latest data to main memory B, the data is read. .

〔Example〕

The present invention will be explained below with reference to FIG. FIG. 1 is a diagram showing the configuration of the present invention in a computer system. In the figure, 1 is a split-type pass line on which control information such as addresses, data, and Read or Write to be given to main storage device B is carried; address information in the path line 1; 3 is data information; 4 is read R or write W information of a control command to the main memory B; 5 is an address determination circuit that determines whether the request is to its own main memory B;
Reference numeral 6 designates the determination result information, 7 designates a request buffer of a first buffer that stores various information 2, 3, and 4 according to the determination result information 6, and 8 designates a memory controller that controls the main storage device B in accordance with various requests. A central processing unit CPUA is connected to the path line 1, and the CPUA accesses the main memory B by issuing various request information via this control circuit. Address ranges are registered in advance. 9 is a circuit for detecting a write request W from the control information 4 stored in the request buffer 7, and 10 is the detection information.

Reference numeral 11 denotes a second store buffer that takes in various pieces of information 2, 3, and 4 according to the detected information.

Reference numeral 12 denotes a request priority determination circuit that specifies and controls the priority of the read request R from the request buffer 7 and the write request W from the store buffer 11, and outputs the request R or W given priority at that time to the memory control 8. Also 2
' is the write request W stored in the store buffer 11
address information. The memory control circuit 8 performs a read or write operation for address 2 in the main memory in accordance with a request from the request priority determination circuit 12.

Reference numeral 15 denotes a match determining unit that compares address 2 for request information 4 from request buffer 7 and address 2' for request information 4 from store buffer 11, and detects whether they match or do not match.

Next, the operation will be explained.

Various requests (R/W) transmitted from cpuA to pass line 1
) is an address accepted by its own main storage device B by the address determination circuit 5. The request buffer 7 receives the judgment result information 6 and takes in various information 2.3.4 from the pass line 1 when the judgment result is true. The request buffer 7 consists of several stages of FIFO-structured buffers, and can take in various types of information 2.3.4 until the buffer is full. request buffer 7
When it becomes full, it transmits information f that it is full to pass line 1. After receiving the information f, CPUA that issues the request refrains from issuing any requests until there is space in the request buffer 7. On the other hand, when the request (R/W) is received in the request buffer 7,
Store it in your own buffer. At this time, in the case of a write request W, the data to be written is also stored in the buffer, so the request buffer 7 quickly becomes full and information f is output.

Next, the request buffer 7 outputs the various kinds of information 2.3.4 taken in in order from the oldest request (R/W). The detection circuit 9 detects the write request W from the control information 4 therein. The store buffer 11 has its detection information 10
is received, and when the detection information is true, the request buffer 7
Address 2, data 3, and write request W4 are separated and fetched.

The store buffer 11 consists of several dozen stages of buffers with an FI l"O structure, and can take in these addresses 2, data 3, and write requests W4 until the buffer is full. Requests that the store buffer 11 has already taken in When the request buffer 7 is full, information g indicating that it is full is transmitted to the request buffer 7.

After receiving this information g, the request buffer 7 stops outputting the write request W information among the various information in the output order, and if the next request is the read request R information, it outputs the information directly to the priority determination circuit 12. Output.

The request priority determination circuit 12 compares and determines the read request R from the request buffer 7 and the write request W coming from the store buffer 1, performs priority control, and prioritizes the read request R over the write request W to perform memory control. As a result, the data at the specified address is read from the main memory B by the read request R from the request buffer 7 and transferred to the pass line 1. Therefore, the request buffer 7 contains the read request information. An empty space corresponding to the output of 11iR is generated, and the next request (R/W) from pass line 1 can be accepted.

However, when the write request W address 2' stored in the store buffer 11 and the address 2 of the read request R from the request buffer 7 are the same, the -match determination unit 15 detects the match and gives priority to requests with -number information. The information is transmitted to the degree determination circuit 12. In this case, there is a read request R from the request buffer 7 and a write request W from the store buffer 11.
The priority of the write request W is inverted by the request priority determination circuit 12, and the write request W is issued to the memory control circuit 8 with priority. This is to prevent old generation data information from being read if the latest data information is not stored in the main storage device B.

The request buffer 7 and the store buffer 11 wait for the completion of processing by the memory control circuit 8 in the main storage device B.
Upon completion of the access process, the following requests are issued to the priority determination circuit 12.

The above process uses request buffer 7 and store buffer 1.
11 is repeated until both internal buffers are empty, that is, until there is no longer a request for its own main memory B.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a first buffer that temporarily stores request information in order, and from this first buffer, reception is performed in order to receive write request information among the request information output. A second buffer is provided that temporarily stores only the request information in order, and if the address of the request information output from the first buffer matches the address of the write request information output from the second buffer, the write request is The information is given priority and sent to the main memory, and in other cases, the read request information that is always output from the first buffer is given priority and sent to the main memory, so that a read request becomes a write request. Since the CPU is not involved much, the necessary data can be transferred at high speed. This improves the efficiency of the entire computer system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a conventional block diagram. ■...Pass line, 2,2...Address, 3...
Data, 4... Control command, 5... Address determination section,
6...Result information, 7...Request buffer, 8.
...Memory control circuit, 9...Detection circuit, 10
...Detection information, 11...Store buffer, 12...
-Request priority determination circuit, 15...matching determination unit, f;
g...-cup information, h...-number information. Agent Masuo Oiwa (2 idiots) Figure 2 1, Indication of the case Patent Application No. 198359 1983 2, Title of the invention 3, Person making the amendment 5C1 Sanka Denki Co., Ltd.: ″′:′: Kei A detailed explanation of the subject invention of the amendment. 6. Contents of the amendment (I + Specification, page 11, line 20, "Issued to 8.")
Insert the following statement after . ``-Number information is write request W to store buffer 11.
Address 2' and read request R from request buffer 7 Write request W information in store buffer 11 that matches address 2 Until the write request W stored in store buffer 11 before is issued to memory control circuit 8 I need iE4 Mokugo! ! I Sugomoro each −
2. Seiyu ÷ - Adultery - Mibuue

Claims (1)

[Scope of Claims] A control method for a main storage device in which a central processing unit accesses the main storage device using read and write request information including a designated address, comprising: a first buffer that temporarily stores the request information in the order in which it is received; A second buffer is provided that temporarily stores only the write request information in the order of reception among the request information output from the first buffer in the order of reception, and an address of the request information output from the first buffer is provided. If the address of the write request information outputted from the second buffer matches, the write request information is sent to the main storage device with priority; otherwise, the write request information is always output from the first buffer. A control method for a main storage device, characterized in that the read request information sent to the main storage device is sent to the main storage device with priority.