JP2001014283A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prepare a shared system cache in a system controller and to make the directly referable to the shared data of the shared system cache without referring to a main storage. SOLUTION: The processors IP0 1-IP3 4 have the caches CS0 11b-CS3 14b and their address management tables TAG0 11a-TAG3 14a respectively. A system controller SC 5 has the copied tables FAA0 11c-FAA3 14c and a shared system cache SCS 17, and the entry of each FAA is provided with an SV bit to show the valid/invalid state of the data stored in the SCS 17. When an access request is inputted from a processor to a shared storage MS 6, the controller SC 5 generates a control signal from a V(valid) bit obtained by referring to every FAA and the SV bit and in response to the access request address, and then controls the V bits of the MS 6 and the SCS 17 and the SV bit according to the generated control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch type computer system having a plurality of processors, and more particularly to a computer system having a shared system cache for transferring data between processors at high speed.

[0002]

2. Description of the Related Art Conventionally, in a computer system having a plurality of processors, in order to increase the throughput of the entire system, the use efficiency of the plurality of processors must be increased.
It is required to reduce the turnaround time of a job. For this reason, in executing a job, a request is satisfied by distributing a plurality of tasks having no dependency among tasks of the job to a plurality of processors and executing the tasks in parallel. When a plurality of tasks are executed in parallel by a plurality of processors, there is a case where it is necessary to refer to shared data shared by a plurality of processors in order to synchronize tasks and refer to data shared between tasks. The transmission and communication of these shared data are generally performed by data in the main storage device, or a dedicated shared register dedicated to shared data is provided on the system controller (see Japanese Patent Application Laid-Open No. 60-37064, the specification). ) Or a dedicated shared storage device (refer to Japanese Patent Application Laid-Open No. 3-228169, refer to the specification). Shared data is placed on a system control device to increase the speed of transmission and communication between processors.

[0003]

However, in the above-described conventional computer system, when the shared data is stored in the main storage device, the main storage device is used for transmitting the shared data among a plurality of processors. Transmission of shared data,
There is a disadvantage that the speed of data transmission and communication is slow because communication is performed. When shared data is placed in a dedicated shared register or a dedicated shared storage device, data transmission and communication speed are improved, but data registration and reference to the dedicated shared register or the dedicated shared storage device are controlled. For this reason, a dedicated control instruction corresponding to the control device (hardware) is required, and there is a drawback in that software support and support are required.

[0004] Such a problem arises in a switch-type computer system in which a plurality of processors and a system controller are connected one-to-one and main memory reference requests from the plurality of processors are made via the system controller. Since it is necessary to store the shared data that passes between the data from a certain processor to the main storage device via the system controller and to pass the shared data on the main storage device again to the processor sharing the data via the system controller. In particular, in a switch-type computer system, the speed of transmission and communication of shared data between processors is particularly slow,
The transmission of data and the securing of communication speed have become major problems. On the other hand, in the case of a bus-type computer system in which a plurality of processors and a system controller are commonly connected by one common data bus, each processor (resource) is connected by one common data bus. Because of the connection, the transmission and communication of data between the processors can be performed directly between the processors via a common data bus. For this reason, in a bus-type computer system, the speed of transmission and communication of shared data between processors does not matter much. However, in the case of a bus-type computer system,
In data transfer, a single common data bus is shared by a plurality of resources. Therefore, there is a problem of insufficient data transfer throughput due to a performance bottleneck of the data bus.

Accordingly, an object of the present invention is to provide a shared system cache using an address management table for managing the memory of a plurality of processors in a system control device in order to solve the above-mentioned drawbacks and problems. An object of the present invention is to provide a computer system capable of directly referring to shared data in a shared system cache without referring to it.

[0006]

In order to achieve the above object, the present invention provides a plurality of processors having a cache, a shared storage device shared by the plurality of processors, and a shared storage device from a plurality of processors. A shared system cache that controls access to the shared processor and stores data shared by a plurality of processors, and transfers data in the shared system cache to the processor in response to a read request for the shared data from the processor. A computer system having a system controller for transferring, the system controller having means for detecting that another processor reads the same data as the data that one processor has in a cache from the shared storage device, Means for storing the data in the shared system cache in response to detection by the means. It has to so that.

Also, a plurality of processors having a cache, a shared storage device shared by the plurality of processors, access to the shared storage device from the plurality of processors is controlled, and data shared by the plurality of processors is stored. A computer system having a shared system cache for storing, and a system controller for transferring data in the shared system cache to the processor in response to a read request for the shared data from a processor, the computer system comprising: The apparatus has a copy of the address management table of each cache, and provides an SV bit indicating validity / invalidity of data stored in the shared system cache in each entry of the copy table. When an access request to a storage device is input, the access request is V bit (Valid for each entry obtained by referring to the table of the respective copy the address
bit) and a control signal generation unit for generating a control signal in the system control device based on the SV bit, and based on the generated control signal, a V bit of the shared storage device and the shared system cache and the table of each copy. And the SV bit.

Further, the control signal generating section is configured to control the OR of the value of the V bit of each entry obtained by referring to the table of each copy by the address of the access request and the SV of each entry. The control signal is obtained by taking the OR of the bit value, the AND of the V bit and the SV bit for each entry, and outputting the control signal obtained by taking the OR of all the AND results.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a switch-type computer system according to an embodiment of the present invention. In FIG. 1, reference numerals 1 to 4 denote processors (Instruction Processors; IP0, IP1, IP2, and IP3), which are all ordinary processing units, 5 is a system controller (SC), and 6 is a plurality of processors.
Main storage device (Main Str shared by IP0-3 (1-4)
age; MS). Also, each processor IP0,
In IP1, IP2, and IP3, caches (Cache; CS0, C) serving as primary storage for storing copies of data in the main storage device MS6
S1, CS2, CS3) 11b, 12b, 13b, 14b and the main memory M stored in the respective caches CS0, CS1, CS2, CS3
The first for cache management in which an address in the main memory of the data in S (6) is registered as an entry address.
Address management table (Tag; TAG0, TAG1, TAG2, TAG3)
11a, 12a, 13a and 14a are provided.

In the system controller SC (5), address management tables TAG0 (11a), TAG1 (12a), TAG2 (13a), TAG3 for cache management in each processor are provided.
(14a) A second address management table (Front Address Array; FAA0, FAA1, FAA2, FA) for cache management in which copies of entry addresses are registered correspondingly.
A3) 11c, 12c, 13c and 14c are provided. In the system controller SC (5), a shared system cache (SCS) 1 for storing only data shared between processors as a copy of data in the main storage device MS (6).
7 are provided. Shared system cache SCS (17)
Is the cache CS0 (11b), CS1 (12
b), has the same memory configuration as CS2 (13b) and CS3 (14b), memory capacity and data storage size (1 block 1
The memory management control of the shared system cache SCS is performed by an SV bit (1 bit) provided in the second address management table FAA.

The second address management table FAA0 (11
c), FAA1 (12c), FAA2 (13c), FAA3 (14c) are TAG0
(11a), TAG1 (12a), TAG2 (13a), TAG3 (14a), and a SV bit (1 bit) for managing data registration in the shared system cache. In the second address management table FAA, the TAG data is referred to as an address management table for checking a store address from another processor, and a memory between the main memory MS (6) and a cache in each processor is referred to. The coincidence control process can be performed at high speed, and at the same time, SCS memory management can be performed to determine whether data corresponding to the address referenced from each processor by the SV bit is registered in the shared system cache SCS.

FIG. 2 shows a data format of an entry address registered in the second address management table FAA. In the second address management table FAA, the entry address data (ADDRESS) portion of bits 1 to 28 for registering the entry address corresponding to the TAG of each processor IP and whether the data stored in the registered entry address is valid A V bit of bit 0 indicating whether or not it is invalid is provided. That is, bit 1
The entry address data (ADDRESS) part of .about.28 and the V bit of bit 0 indicating whether the data stored in the registered entry address is valid or invalid are the same as the contents of the TAG entry. In addition, the shared system cache SCS
SV of bit 30 indicating whether the data registered to
Bits and entire entry address data (bits 0 to 30)
Is provided with a P bit (parity bit) of bit 31 for guaranteeing the parity. Thus, each entry of the second address management table FAA is configured.

If the V bit (bit 0) of the entry data registered in the second address management table FAA is "1", the data stored in the entry address indicated by the ADDRESS of bits 1 to 28 is valid. There is one block (128 bytes) of data corresponding to this entry address, and the corresponding processor IP cache CS (11b, 12b, 13b, 14)
b) indicates that the data is registered as a copy of data from the main storage device MS (6). If the V bit (bit 0) is “0”, the data stored in the entry address indicated by the ADDRESS of bits 1 to 28 is invalid, and the cache CS (11b, 12b, 13b, 13b, No valid data is registered in 14b). Also, the S of the entry data registered in the second address management table FAA
The V bit (bit 30) is also significant when the V bit (bit 0) is "1". That is, when the V bit (bit 0) is “1” and the SV bit (bit 30) is “1”, bits 1-2
One block of data corresponding to the data stored at the entry address indicated by the ADDRESS of 8 is stored in the shared system cache SCS (17) simultaneously with the corresponding processor IP cache CS (11b, 12b, 13b, 14b). Is also registered. That is, when the V bit = “1” and the SV bit = “1”, the data of one block stored in the entry address ADDRESS is shared with the cache CS of the corresponding processor IP as a copy of the data in the main storage device MS. It is registered in both the system cache SCS. When the V bit (bit 0) is “1” and the SV bit (bit 30) is “0”, the data stored in the cache CS is not registered in the shared system cache SCS and the shared system cache SCS is not registered. Is not valid, and the data is registered only in the cache CS of the processor IP corresponding to the V bit = “1”. When the V bit (bit 0) is “0”, the entry address indicated by ADDRESS (bits 1 to 28) is not valid, and the SV bit (bit 30) is not valid.

The processor IP having the cache CS registers the data to be used in the cache CS as a copy of the main memory MS, and the processor IP always refers to the data registered in the cache CS without referring to the main memory MS. This reduces the overhead of referring to the main memory MS. Here, in a computer system in which a plurality of processors including the cache CS share the main memory MS, the plurality of processors operate asynchronously, and necessary reference to the main memory MS is processed in parallel. Conventionally, the parallel reference of the main memory MS from each processor IP is switch-controlled by the system controller SC, the main memory MS reference requests from each processor IP are ordered, and the main memory data is sequentially referred to for each request. . At this time, the system controller S
C performs memory matching control between caches CS of each processor IP according to the reference order of the main memory MS. For this reason,
The system control device SC has a second address management table FA
A is provided, and when the main memory MS is written, the cache CS is invalidated by changing the main memory MS data. When the main memory MS is read, the cache CS is validated by registering the main memory MS data with the cache CS. I am doing it.

Here, in a computer system having a plurality of processors, in order for the plurality of processors to operate efficiently in parallel, synchronous processing of the processors is essential, and data transmission, communication, communication between processors operating asynchronously. There is also a demand for sharing data between processors.
However, in the case of the conventional computer system, the data shared between the processors is stored in the main memory MS far from the processor.
Therefore, the overhead is large for reference, and even if it is registered in the cache CS, cache registration and cache invalidation frequently occur between processors due to rewriting between multiple processors. Memory ms
A reference to has occurred.

Here, the present invention focuses on the second address management table FAA, and in order to solve the above-mentioned problem, a shared system cache SCS (17) is provided to manage the memory of the shared system cache SCS (17). An SV bit is provided in the second address management table FAA to perform memory management of the shared system cache SCS. The memory management method of the shared system cache SCS adopts a store-in method, and the shared data that has been referred to most recently is always registered in the shared system cache SCS. Note that the store-in method is a method in which write data is written only to the cache memory, and the contents of the cache memory are collectively written to the main storage device later.

Next, the control of the shared system cache SCS will be specifically described with reference to FIGS.
FIG. 3 is an example of a detailed block diagram of a control signal generation unit that generates a control signal in the system control device SC by referring to the second address management table FAA having an SV bit in the system control device SC. Reference numeral 7 denotes a register indicating the main memory MS reference address issued from each processor IP. The second address management table FAA is referred to by the address set in the address register (7), and the memory matching control of the cache CS and the reference of the shared system cache are performed. In the case of reading data by IP, when data is stored in the cache CS of this IP, the system controller S
No request is made to C for the above reference. When a request for referring to the main memory MS is issued from the processor IP, the main memory MS reference address is set in the address register (7).
The main memory MS reference address set in the address register (7) includes a tag address (corresponding to the entry address data (ADDRESS) of bits 1 to 28 in FIG. 2) and an address (block address) designating a block. . The block address specifies one of a plurality of entries (corresponding to each block) specified by the address of the tag in the FAA. Each FAA is referred to by the address set in the address register (7).

Here, FAA0 (1) corresponding to processor IP0
Regarding 1c), the address signal (30) of the address set in the address register (7) is compared with the entry address signal (321) of FAA0 (11c), and if they match, the address comparison signal (341) is It becomes “1”. Also, F specified by the block address of the address register (7)
The V bit signal (311) of the entry of AA0 (11c) (the entry corresponding to the block address) becomes “1” if the data of the designated block is valid. Then, an AND of the address comparison signal (341) and the V bit signal (311) is taken,
Get FAA hit signal (351). Further, the FAA0 hit signal (351) is the SV bit signal (3) of the entry of FAA0 (11c) specified by the block address of the address register (7).
ANDed with 11), shared system cache SCS (17)
, An SV hit signal (361) of FAA0 indicating that data is registered. The FAA0 SV hit signal (361)
When "1", it indicates that the registration data of the shared system cache SCS is valid. FAA1 (12c), FAA2 (13
c), FAA3 (14c) has the same logic circuit as FAA0 (11c), and similar FAA reference is possible. Also, each FAA0
~ The FAA hit signals (351, 352, 353, 354) of FAA3 are ORed and the signal FAA Hit (37) and the SV hit signals (361, 362, 363, 364)
OR signal SV Hit (39), SV bit signal (331, 332, 333, 33
4) The OR signal SV Bit (38) is generated, and the FAA registration control including the registration of the shared system cache SCS is performed by these signals.

FIG. 4 shows FAA Hit (37), SV Bit (38), SV
Hit (39) in the bit state of each signal, data read case and write case processing for the main memory MS, processing for the shared system cache SCS, and F
FIG. 11 is a diagram showing, by a table, the settings of the FAA entry, V bit, and SV bit as AA processing as processing at the request issuing source and processing at a source other than the request issuing source. The request issuance of an access request to the main storage.

In the data read case, FAA Hit (37)
When = "0", no shared data is detected, so SV Bit (38) = "0" and SV Hit (39) = "0" regardless of the presence or absence of data in the shared system cache SCS. In the same manner as the conventional MS reference request, a read request is issued to the MS and the FAA registration process is performed.
That is, the data read in response to the issued read request is stored in the request issuing CS, and the request issuing FAA registration changes the V bit from “0” to “1” and sets the SV bit to “0”. Leave.

FAA Hit (37) = “1” and SV Bit (38) =
When reading data with “0” and SV Hit (39) = “0”, FAA
Since Hit (37) = "1", it can be seen that the data of the same entry address has already been stored in any of the processors IP0-3 corresponding to FAA0-FAA3 (automatically detected). Moreover, since SV Bit (38) = "0", no data is registered in the shared system cache SCS.
For this reason, data is read out to the MS,
The read data is the cache CS of the request issuer
As well as the shared system cache SCS. At this time, for an IP that hits the FAA and has already registered the shared data, the SV bit of the corresponding FAA is changed from “0” to “1” by registering the shared data in the SCS. In addition, the V bit and the SV bit of the FAA corresponding to the request source IP are changed from “0” to “1”. Further, the IP for which the shared data has already been registered can be identified by which of the FAA hit signals (351, 352, 353, 354) is “1”. By the above processing, data sharing between processors is automatically detected and the shared system cache is
You can register with SCS.

FAA Hit (37) = “1” and SV Bit (38) =
When reading “1” and SV Hit (39) = “1”, SV Hit
(39) Since "1", the data corresponding to the read address has already been registered in the shared system cache SCS. For this reason, data is read from the shared system cache SCS. Shared system cache S
Data is registered from the CS to the cache CS, and at the time of FAA registration, the V bit and the SV bit are changed from “0” to “1”. By the above processing, data shared between the processors can be read at high speed from the shared system cache SCS without referring to the main memory MS.

Next, in the data write case, FAA Hit (3
7) When “0”, since shared data is not detected, SV Bit (38) = “0” and SV Hit (39) = “0” regardless of the presence or absence of data in the shared system cache SCS. , And issues a write request to the MS in the same manner as the conventional MS reference request to perform the MS write process.

FAA Hit (37) = "1" and SV Hit (39) = "0"
Since the data corresponding to the write address is not registered in the shared system cache SCS because SV Hit (39) = “0” when writing the data of, regardless of the existence of data in the shared system cache SCS, SV Bit (3
8) = “0”, a write request is issued to the MS in the same way as the conventional MS reference request, and the FAA is invalid because the data is changed by writing the MS to the IP that hit the FAA. Perform the conversion process. Regarding the FAA invalidation processing, the V bit of the FAA is changed from “1” to “0”.

FAA Hit (37) = "1", SV Bit (38) =
When SV Hit (39) = “1” data is written with “1”, the following processing is performed depending on whether or not the request issuing source is a FAA hit in this case. When the request source is an IP that is not a FAA hit After writing the write data to the SCS, write the SCS data to the MS. In addition, the write-processed data is invalidated for the SCS. FAA and SCS are invalidated for IP that hit FAA, not the request source. That is, V and SV are changed from “1” to “0”. If the request source is the FAA hit IP, issue a write request to the SCS and transfer the data to the SCS
Write to. For the IP that issued the request, V =
Leave "1" and SV = "1" as they are. FAA and SCS for IPs that hit FAA instead of request originator
Invalidate. That is, V and SV are changed from “1” to “0”.

By performing the above processing, data to be shared between the processors can be automatically selected and registered in the shared system cache SCS without software intervention. It is possible to transmit and communicate shared data at high speed. In addition, it has been explained that the shared data is automatically detected and registered in the shared system cache SCS without software intervention, but the data to the shared system cache SCS is provided while having the feature of automatically detecting and registering the shared data. Providing a dedicated instruction to force registration does not depart from the invention. As described above, the present invention has been specifically described based on the example of the embodiment. However, the present invention is not limited to the embodiment, and various changes can be made without departing from the gist thereof. Needless to say, there is.

[0027]

As described above, according to the present invention,
The problem of low data transmission and communication speeds shared by multiple processors can be solved by introducing a shared system cache in the system controller. In addition, the turnaround time of the job can be reduced. In addition, regarding data fetching into the shared system cache, sharing of data among a plurality of processors can be automatically detected, and only the detected data can be automatically fetched into the shared system cache without software intervention.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a configuration of a computer system according to the present invention.

FIG. 2 is a diagram showing a data format of an entry address registered in an address management table FAA.

FIG. 3 is a block diagram showing a configuration of a control signal generator of an address management table FAA.

FIG. 4 is a table showing processing contents for a main memory MS, a shared system cache SCS, and an address management table FAA corresponding to a control signal from a control signal generation unit.

[Explanation of symbols]

1,2,3,4 processor (IP0, IP1, IP
2, IP3) 5 System controller (SC) 6 Main storage (MS) 11a, 12a, 13a, 14a First address management table (TAG0, TAG1, TAG2, TAG3) 11b, 12b, 13b, 14b Cache (CS)
0, CS1, CS2, CS3) 11c, 12c, 13c, 14c Second address management table (FAA0, FAA1, FAA2, FAA3) 17 Shared system cache (SCS) 7 Address register 331, 332, 333, 334 SV bit signal 351, 352, 353, 354 FAA hit signal 361, 362, 363, 364 SV hit signal 37 FAA Hit 38 SV Bit 39 SV Hit

Claims (3)

[Claims] 1. A plurality of processors having a cache, a shared storage device shared by the plurality of processors, and a data shared by the plurality of processors for controlling access to the shared storage device from the plurality of processors. A shared system cache that stores a shared system cache, and a system controller that transfers data in the shared system cache to the processor in response to a read request for the shared data from a processor, the computer system comprising: The controller has means for detecting that another processor reads the same data as the data that one processor has in the cache from the shared storage device, and stores the data in the shared system cache in response to the detection by the means. A computer system comprising means for performing: 2. A plurality of processors each having a cache, a shared storage device shared by the plurality of processors, and controlling access to the shared storage device from the plurality of processors to store data shared by the plurality of processors. A computer system having a shared system cache for storing, and a system controller for transferring data in the shared system cache to the processor in response to a read request for the shared data from a processor, wherein the system control The apparatus has a copy of the address management table of each cache, and each entry of the copy table indicates whether the data stored in the shared system cache is valid / invalid.
A V bit is provided, and when an access request to the shared storage device is input from the processor, a V bit (Valid bit) of each entry obtained by referring to the table of each copy by the address of the access request. A control signal generation unit for generating a control signal in the system control device based on the SV bit, based on the generated control signal, a V bit and an SV bit of the shared storage device, the shared system cache, and the table of each copy; A computer system characterized by performing control of: 3. The computer system according to claim 2, wherein the control signal generation unit ORs the value of the V bit of each entry obtained by referring to the table of each copy by the address of the access request. A control signal, a control signal obtained by ORing the value of the SV bit of each entry, and a control signal obtained by ANDing the V bit and the SV bit for each entry, and ORing all the AND results A computer system characterized by the following.