JPS57164363A - Simulation system in multi-processor system - Google Patents

Simulation system in multi-processor system

Info

Publication number
JPS57164363A
JPS57164363A JP5037581A JP5037581A JPS57164363A JP S57164363 A JPS57164363 A JP S57164363A JP 5037581 A JP5037581 A JP 5037581A JP 5037581 A JP5037581 A JP 5037581A JP S57164363 A JPS57164363 A JP S57164363A
Authority
JP
Japan
Prior art keywords
processor
reception
transmission
address
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5037581A
Other languages
Japanese (ja)
Other versions
JPH0315778B2 (en
Inventor
Atsushi Sugano
Kenichi Ueda
Kunio Honda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5037581A priority Critical patent/JPS57164363A/en
Publication of JPS57164363A publication Critical patent/JPS57164363A/en
Publication of JPH0315778B2 publication Critical patent/JPH0315778B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To control transmission/reception of a simulation data, by comparing the address of a processor connected to a common bus with a processor address designating the transmission/reception with the processor. CONSTITUTION:An address of a processor connected to a common bus 1 is stored in a processor execution table 6. A part of a simulation data 7 is stored in a processor address 8 designating the transmission/reception, the address of a processor existing table 6 and that of the processor address 8 are compared at a comparison circuit 9, if the transmission of the simulation 7 to the existing processor connected to the common bus 1 or the reception of data from the processor is made, is discriminated, and the data is outputted to the common bus 1 via a transmission gate 10 and a transmission buffer in case of transmission, and if the reception data inputted via a reception buffer 5 is equal to the simulation data 7 in case of reception is checked at a coincidence circuit 12, and the result is given to a reception status 13 via a gate 11.
JP5037581A 1981-04-02 1981-04-02 Simulation system in multi-processor system Granted JPS57164363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5037581A JPS57164363A (en) 1981-04-02 1981-04-02 Simulation system in multi-processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5037581A JPS57164363A (en) 1981-04-02 1981-04-02 Simulation system in multi-processor system

Publications (2)

Publication Number Publication Date
JPS57164363A true JPS57164363A (en) 1982-10-08
JPH0315778B2 JPH0315778B2 (en) 1991-03-01

Family

ID=12857128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5037581A Granted JPS57164363A (en) 1981-04-02 1981-04-02 Simulation system in multi-processor system

Country Status (1)

Country Link
JP (1) JPS57164363A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161737A (en) * 1983-03-04 1984-09-12 Hitachi Ltd Microprocessor system
JPH01207838A (en) * 1988-02-16 1989-08-21 Fujitsu Ltd Parallel logic simulation control system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141759A (en) * 1981-02-26 1982-09-02 Nec Corp Data processing system
JPS57143669A (en) * 1981-02-28 1982-09-04 Omron Tateisi Electronics Co Debugging device for multiprocessor system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141759A (en) * 1981-02-26 1982-09-02 Nec Corp Data processing system
JPS57143669A (en) * 1981-02-28 1982-09-04 Omron Tateisi Electronics Co Debugging device for multiprocessor system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161737A (en) * 1983-03-04 1984-09-12 Hitachi Ltd Microprocessor system
JPH0565894B2 (en) * 1983-03-04 1993-09-20 Hitachi Ltd
JPH01207838A (en) * 1988-02-16 1989-08-21 Fujitsu Ltd Parallel logic simulation control system

Also Published As

Publication number Publication date
JPH0315778B2 (en) 1991-03-01

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