JPH0315778B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a multiprocessor system in which a plurality of processors are connected to one common bus.
The present invention relates to a simulation device for simulating the functions of one or more processors.

Conventionally, this type of simulator used a method in which simulations were performed in the order in which the simulation data was prepared at the time of execution, so whenever the actual configuration of the processor was changed, the simulation data was updated accordingly. The disadvantage was that it required preparation of

The prior art will be further described below with specific examples.

It is assumed that a certain system (for example, a traffic control system) consists of four boards each having processors A, B, C, and D as main components. If four researchers A, B, C, and D develop this separately based on the specifications, development will be completed in the order of A, B, C, and D based on the development content (difficulty of development). If you have an idea, the simulation data should be first the simulation for A, then the simulation for A+B, then the simulation for A+B.
The data is set so that simulation for +C and finally simulation for A+B+C+D are performed. However, if the development of B is delayed for some reason, or if there is a change in the specifications of part of B that does not affect A, C, or D, you will have to wait for the completion of B. In this case, simulations of C and D cannot be performed. The development of C and D was completed first, then the development of B was completed, and as a result of running the simulation for A + B + C + D, there was a mistake in one of C and D, and one of C and D had to be redeveloped. In such a case, there is a big loss in terms of deadline.

The present invention aims to eliminate these drawbacks and provide a general-purpose multiprocessor system simulation device that is capable of simulating independently of the configuration of existing processors. In a multiprocessor system, a simulation device for a multiprocessor system that operates at a predetermined timing in synchronization with a clock, the processors of the existing processors connected at the present time are connected to a common bus to which multiple processors are commonly connected. A processor existence table that stores processor addresses, and simulation data that is the same as the data sent and received between the multiprocessor systems when completed.
a storage means for storing a transmitting processor address of a processor to be transmitted in pair with the data and a receiving processor address of a processor to be received; and before the simulation data is transmitted onto the common bus. comparing the processor address stored in the processor existence table with the transmission processor address sent from the storage means at a predetermined timing to determine the existence of the processor to be transmitted; Before receiving the simulation data being sent out on the common bus, the processor address stored in the processor existence table and the receiving processor address sent out from the storage means at a predetermined timing. a comparison circuit that determines the existence of a processor to which the data should be received by comparing the data; and when it is determined by the comparison circuit that the processor to which the data should be sent does not exist, a comparison circuit that determines the existence of the processor to which the data should be sent is determined based on the address of the sending processor stored in the storage means; sending simulation data to the common bus;
On the other hand, if it is determined that the processor exists, the transmission gate means prevents the sending of the simulation data, and if the comparator circuit determines that the processor to receive the data does not exist, it outputs the reception status; , when it is determined that the processor to receive the data exists, it blocks the output to the reception status, and at the same time, outputs the simulation data stored in the storage means to the simulation data input via the common bus. The apparatus is provided with reception matching/gate means for determining whether or not to output the result to the reception status after checking the matching state of the data with the reception data.

FIG. 1 shows the configuration of a multiprocessor system to which the present invention is applied, in which a plurality of processors 21, 22,...2N and a simulator 3 are connected to a common bus 1. Data prepared in advance is transmitted and received to and from the processors 21, 22, . . . 2N via the processors 21, 22, .

FIG. 2 shows an example of the configuration of the simulator 3 used in the present invention, and the details of the present invention will be explained below in accordance with this figure.

1 is a common bus, 4 is a transmission buffer to the common bus, and 5 is a reception buffer. Addresses of processors connected to the common bus 1 are held in a processor existence table 6.

On the other hand, each simulation data 7 is stored in the storage section in association with each processor address 8 specifying transmission and reception. Figure 3 shows the data format. As shown in the figure, the receiving processor address and the transmitting processor address 8 are included in the data transmitted and received with the common bus 1 along with the simulation data 7, and the simulator 3
is configured to be able to receive all data on the common bus 1. The comparison circuit 9 compares the address of the processor existence table 6 with the address of the processor address 8, and determines whether to send the simulation data 7 to the existing processor connected to the common bus 1 or to send the data from the existing processor. The transmission gate 10 or the reception gate 11 is controlled accordingly.

Next, the operation will be explained. First, the address of the processor existence table 6 and the contents of the processor address 8 are compared in the comparison circuit 9, and it is determined whether or not the transmitting processor exists. When a transmitting processor exists, the transmitting gate 10 is closed, the simulation data 7 is not transmitted, and the data of the existing transmitting processor is taken into the common bus 1.
On the other hand, when the transmitting processor does not exist, the transmitting gate 10 is opened by the output of the comparison circuit 9 and the simulation data 7 is outputted to the common bus 1 via the transmitting buffer 4. In this way, data is present on the common bus 1.

On the other hand, the reception buffer 5 always takes in data on the common bus 1. Then, the address of the processor existence table and the contents of the processor address 8 are compared by a comparison circuit 9, and it is determined whether or not the receiving processor exists. If a receiving processor exists, the receiving gate 11 is closed, and the data on the common bus 1 is only sent to the receiving processor for processing, but the result is not sent to the receiving status 13. On the other hand, if it does not exist, the reception gate 11 is opened by the output of the comparison circuit 9,
The matching circuit 12 checks whether the data loaded into the receiving buffer 5 and the simulation data 7 are equal (however, the matching circuit 12 always checks whether the receiving processor actually exists or not). ) is passed through the reception gate 11 and stored in the reception status 13 as a bit representing the state. The received data and simulation data are compared to see if the actual received data is equal to the received data prepared in advance. A confirmation will be made.

The confirmation of existing processors is as follows. That is, if there is a malfunction in the existing processor, the result received in the reception status 13 will naturally be different from the original result. Or, it can be predicted that this possibility is high. In such cases, to find the processor that caused the malfunction,
The processor that is most likely to have malfunctioned among the existing processors is predicted based on the contents stored in the reception status 13, and the processor is separated from the system and the simulation of the present invention is performed again to calculate the result (stored in the reception status 13). All you have to do is check the contents (the content provided).

The more specific operation of the simulation method of the present invention described above is shown in FIG. 1 and FIG. 3b.
This will be explained with reference to.

In the following explanation, it is assumed that the system has four processors 21, 22, 23, and 24 in FIG. 1, of which 23 processors are missing in the system. Therefore, the processor existence table 6 holds three processor addresses 21, 22, and 24. On the other hand, the simulation data 7 stored in the storage section all have a data length of "1" as shown in FIG. 3b.
(However, in each simulation data 7, each reception processor address and transmission processor address are stored in correspondence), and each processor 21, 2
2 and 24 hold the same simulation data regarding their own transmission, and perform corresponding certain processing regarding reception. Also, it is assumed that the entire system is synchronized.

(1) Handling of simulation data First, the simulation data, that is,
The receiving processor address "22" and the transmitting processor address "21" are sent to the comparator circuit 9, and the data length "1" and data "A" corresponding to each address are sent from the storage section to the transmitting gate 1.
0, and sent to match circuit 12.

The comparison circuit 9 uses the received processor address ``22'' and the transmitted processor address ``21'' to check whether or not the processor pointed to by each address actually exists on the system, while referring to the processor existence table 6. . the result,
Since the transmission processor 21 exists, the transmission gate 10 is closed and the data length "1" and data "A" are
is not sent to the transmission buffer 4 and therefore not sent to the common bus 1.

During this time, the existing processor 21 is sending simulation data onto the common bus 1 to the also existing processor 22.

The sent simulation data is received by the existing processor 22 and subjected to certain processing, and is also received by the reception buffer 5 of the simulator 3. The matching circuit 12 compares the simulation data sent out in advance from the storage section with the output of the receiving buffer 5 (specifically, the data corresponding to both data A), and determines if they match.
The mismatch state is output as information such as a flag.

By the way, in advance, the comparison circuit 9 refers to the processor existence table 6 regarding the receiving processor address "22" to check whether the processor pointed to by the address actually exists on the system, and as a result, the receiving processor 22 Therefore, the receiving gate 11 is closed and the matching circuit 1
The result of 2 is not sent to the reception status 13.

After this series of processing is completed, proceed to the next step.

(2) Handling of simulation data Next, consider the simulation data, that is,
The receiving processor address "23" and the transmitting processor address "22" are sent to the comparator circuit 9, and the data length corresponding to each address is "1".
and data "B" are sent from the storage section to the transmission gate 10 and the matching circuit 12.

The comparison circuit 9 uses the received processor address "23" and the transmitted processor address "22" to refer to the processor existence table 6 to check whether the processor pointed to by each address actually exists on the system. . the result,
Since the transmission processor 22 exists, the transmission gate 10 is closed and the data length "1" and the data "B" are transmitted.
is not sent to the transmission buffer 4 and therefore not sent to the common bus 1.

During this time, the existing processor 22 is sending simulation data onto the common bus 1 to the non-existent processor 23.

Since the processor 23 does not exist, this sent simulation data row is processed by the simulator 3.
It is received only by the receiving buffer 5 of . Matching circuit 1
In step 2, the simulation data row sent out in advance from the storage unit is compared with the output of the receiving buffer 5 (specifically, the data corresponding to both data B), and the match or mismatch status is output. .

By the way, in advance, the comparison circuit 9 checks whether or not the processor pointed to by the address actually exists on the system by referring to the processor existence table 6 regarding the receiving processor address "23", and as a result, the receiving processor 23 Since it is not present, the receive gate 11 is open and the result of the matching circuit 12 is sent to the receive status 13.

After this series of processing is completed, proceed to the next step.

(3) Handling of simulation data Next, the simulation data, that is, the receiving processor address "24" and the transmitting processor address "23" are sent to the comparator circuit 9, and each of the addresses Data length “1” and data “C” corresponding to the data length “1” and data “C” are sent from the storage section to the transmission gate 10 and the matching circuit 12.

The comparison circuit 9 uses the received processor address "24" and the transmitted processor address "23" to refer to the processor existence table 6 to check whether the processor pointed to by each address actually exists on the system. . the result,
Since the transmission processor 23 does not exist, the transmission gate 10 is opened and the data length "1" and the data "C" are transmitted.
is sent to the common bus 1 via the transmission buffer 4.

Since the processor 23 does not exist, only the simulation data sent from the simulator 3 to the processor 24 is transferred to the common bus 1.
exists above.

The sent simulation data is received by the existing processor 24 and subjected to certain processing, and is also received by the reception buffer 5 of the simulator 3. The matching circuit 12 compares the simulation data C sent from the storage unit in advance with the output of the receiving buffer 5 (specifically, the data corresponding to both data C), and determines whether they match or not.
Outputs mismatch status.

By the way, in advance, the comparison circuit 9 refers to the processor existence table 6 regarding the receiving processor address "24" to check whether the processor pointed to by the address actually exists on the system.As a result, the receiving processor 24 Since it is present, the receive gate 11 is closed and the result of the matching circuit 12 is not sent to the receive status 13.

(4) Treatment of simulation data Next, the simulation data, that is,
The receiving processor address "21" and the transmitting processor address "24" are sent to the comparator circuit 9, and the data length "1" and data "D" corresponding to each address are sent from the storage section to the transmitting gate 1.
0, and sent to match circuit 12.

The comparison circuit 9 uses the received processor address ``21'' and the transmitted processor address ``24'' to check whether or not the processor pointed to by each address actually exists on the system, while referring to the processor existence table 6. . the result,
Since the transmission processor 24 exists, the transmission gate 10 is closed and the data length "1" and the data "D" are
is not sent to the transmission buffer 4 and therefore not sent to the common bus 1.

During this time, the existing processor 24 is sending simulation data onto the common bus 1 to the also existing processor 21.

The sent simulation data is received by the existing processor 21 and subjected to certain processing, and is also received by the reception buffer 5 of the simulator 3. The matching circuit 12 compares the simulation data D sent out in advance from the storage section with the output of the receiving buffer 5 (specifically, the data corresponding to both data D), and determines whether they match or not.
Outputs mismatch status.

However, in advance, the comparison circuit 9 refers to the processor existence table 6 regarding the receiving processor address "21" to check whether the processor pointed to by the address actually exists on the system, and as a result, the receiving processor 21 Since it is present, the receive gate 11 is closed and the result of the matching circuit 12 is not sent to the receive status 13.

Since this embodiment has such a structure, the data prepared for the simulator can be prepared independently of the multiprocessor configuration, and input/output operations with the simulator are automatically determined by the external processor configuration. be done.

As described above, it is expected that multiprocessor systems based on microprocessors will be used in many fields in the future. It can be said that the industrial value of the simulation device is great because of the ease with which simulation data can be prepared and the versatility of simulation operations.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a multiprocessor system configuration to which the present invention is applied, Fig. 2 is a block diagram showing an example of the configuration of a simulator used in the present invention, and Fig. 3 is a block diagram showing an example of the configuration of a simulator used in the present invention. FIG. 2 is a diagram showing an example of a data format on a common bus. 1... common bus, 3... simulator, 4...
Sending buffer, 5...Receiving buffer, 6...Processor existence table, 7...Simulation data, 8...Sending/receiving processor address, 9...
Comparison circuit, 10...Transmission gate, 11...Reception gate, 12...Coincidence circuit, 13...Reception status, 21, 22,...2N...Processor.

Claims (1)

[Scope of Claims] 1. In a simulation device for a multiprocessor system that operates at a predetermined timing in synchronization with a clock, a plurality of processors are currently connected to a common bus that is commonly connected. a processor existence table that stores the processor addresses of existing processors; and simulation data that is the same as the data sent and received between the multiprocessor systems when completed.
a storage means for storing a transmitting processor address of a processor to be transmitted in pair with the data and a receiving processor address of a processor to be received; and before the simulation data is transmitted onto the common bus. comparing the processor address stored in the processor existence table with the transmission processor address sent from the storage means at a predetermined timing to determine the existence of the processor to be transmitted; Before receiving the simulation data being sent out on the common bus, the processor address stored in the processor existence table and the receiving processor address sent out from the storage means at a predetermined timing. a comparison circuit that determines the existence of a processor to which the data should be received by comparing the data; and when it is determined by the comparison circuit that the processor to which the data should be sent does not exist, a comparison circuit that determines the existence of the processor to which the data should be sent is determined based on the address of the sending processor stored in the storage means; sending simulation data to the common bus;
On the other hand, if it is determined that the processor exists, the transmission gate means prevents the sending of the simulation data, and if the comparator circuit determines that the processor to receive the data does not exist, it outputs the reception status; , when it is determined that the processor to receive the data exists, it blocks the output to the reception status, and at the same time, outputs the simulation data stored in the storage means to the simulation data input via the common bus. 1. A simulation device for a multiprocessor system, comprising reception matching/gate means for determining whether or not to output the result to the reception status after checking the state of data matching with the processing data.