JPH0520783B2 - - Google Patents

Description

[Detailed description of the invention]

[Object of the Invention] (Industrial Application Field) The present invention relates to a parallel processing system formed by combining a large number of processors, and particularly to a parallel processing system equipped with a broadcast transfer function for transferring the same data to a plurality of processors. Regarding. (Prior Art) Various parallel processing systems comprising a large number of processors have been proposed. As shown in FIG. 6, this system basically consists of a plurality of processors 201 to 204 interconnected via a coupling means 200, with each processor 201
204 mutually transfer data via this coupling means 200. At this time, the information transferred between the processors via the coupling means 200 is usually
As shown in the figure, V section 301, A section 302, PN
It consists of a section 303 and a data section 304.
The V section 301 and the A section 302 are control fields, and the V section 301 receives a control signal indicating that data is being transferred, and the A section 302 receives a response signal from the transfer destination processor. In other words, when V=1, data is being transferred and indicates that the data should be accepted. Further, if A=1, it indicates that data has been received. Also,
A forwarding address is given to the PN section 303,
Data to be transferred is assigned to the data section 304. By the way, in such a parallel processing system,
Broadcast transfers may be required to send the same data from one processor to multiple other processors. Without this broadcast transfer function, the same data would be sent repeatedly to each necessary processor, leading to a decrease in system efficiency. Therefore, as a method that can be implemented relatively easily, a control bit for instructing broadcast transfer is newly added to the information shown in Figure 7, and when this control bit is "1", all processors are notified that broadcast transfer is being performed. A method is being considered in which the system makes a decision and the data is imported at the same time. However, this method has the disadvantage that it is not possible to selectively perform broadcast transfer to some specific processors. On the other hand, when the number of processors configuring a parallel processing system increases, a plurality of programs may be simultaneously executed by a plurality of processors to advance processing. For example, as shown in FIG.
4 to 317, 318, and 319 each execute other programs, but even in this case, it is impossible to effectively perform broadcast transfer only between processors that execute one program. Ta. Furthermore, even within one program, as the processing progresses, a portion of the processing may be executed by a plurality of processors, as shown in FIG. 9, for example. In the figure, four program modules 401, 402, 403, 4 are generated from the main program 400.
04 are activated and run on separate processors, and furthermore, program module 401 executes programs 405 to 407, and program module 403 executes operations on separate processors.
408, 409, program module 40
4 starts 410 to 412. In this case, between the activated programs, for example 401-404, 405-407, 408-40
When broadcast transfer is required between 9,410 and 412, it is necessary to divide the processors into arbitrary groups and perform broadcast transfer between the divided processors. Similarly, it was impossible to perform broadcast transfer efficiently. (Problems to be solved by the invention) As mentioned above, in conventional parallel processing systems,
Broadcast transfer cannot be performed between a plurality of arbitrarily selected processors, resulting in a problem that data transfer efficiency is reduced. The present invention was made to solve this problem, and in a parallel processing system in which multiple processors are combined, it is possible to perform broadcast transfer between arbitrary processors, thereby improving data transfer efficiency. The purpose is to provide a parallel processing system. [Structure of the Invention] (Means for Solving Problems) In the present invention, each processor is provided with block number storage means. This block number storage means stores a number (block number) that specifies a group of processors that receive common data during broadcast transfer. Also,
The processor includes a comparison means for comparing the block number stored in the block number storage means with the block number sent from the sender's processor, and a comparison means for comparing the block number stored in the block number storage means with the block number sent from the sender's processor. Means for receiving data from the processor is provided. (Function) In the present invention, a plurality of processors are divided into arbitrary groups, a block number is assigned to each group to identify the group, and the block number storage means of each processor is stored with a block number specified by, for example, the sender's processor. By storing an arbitrary block number based on the block number, it is possible to specify which group the processor belongs to based on this block number. Then, by specifying the block number as a transfer destination address, the sender processor can broadcast-transfer the same data to a group of processors that store the same block number. (Example) Hereinafter, a parallel processing system according to an example of the present invention will be described with reference to the drawings. As shown in FIG. 1, this system is constructed by connecting a plurality of processors 11-14 capable of parallel processing via a plurality of buses 21-27 serving as coupling means. Here, the bus 21 is a data bus, and the bus 22 is an address bus for transferring a transfer destination processor number or a block number specifying a transfer destination processor group. The bus 23 is a signal line that transfers information indicating that the data, processor number, or block number is being transferred on these buses 21 and 22 with a "1". This is a signal line that transfers information that becomes "1" when retransmitting. The bus 25 is a signal line that conveys a response from the processor specified by the address bus 22, and when the specified processor is "1"
Make it. The bus 26 indicates that data has been sent but cannot be received when the receiving processor is not yet in a position to receive the data, such as when there is still data in the buffer register. This is a signal line that sends information. Furthermore, the bus 27 is a signal line that transfers information that becomes "1" when some error is detected in the data received by the receiving processor. That is, the buses 21 to 24 are used to transfer various information from the sender's processor to the receiver's processor, and the buses 24 to 27 are used to transfer response information from the transfer destination processor specified by the bus 22. used for During broadcast transfer, a block number common to a plurality of processors is given to address bus 22, so the response signals transferred via each of the buses 24 to 27 are wired-ORed. That is, if there is even one processor that sets a signal line to "1", that signal line becomes "1". Each of the processors 11 to 14 has a sender function and a receiver function.
Therefore, any of the processors 11 to 14 can act as a sender, but two or more processors cannot act as senders at the same time. The processor that will be the data sender is determined using a well-known determination method. Next, the operation of one of the processors that is a data sender will be explained. This processor outputs the transfer destination processor number or block number to the address bus 22, and also outputs the transmission data to the data bus 21. Additionally, this processor sets the bus 23 to "1" to indicate that data is being sent. Thereafter, the processor monitors the buses 25, 26, and 27, and determines that data has been transferred correctly if the buses 25, 26, and 27 become (1, 0, 0). bus 25,2
If 6, 27 becomes (1, 0, 0), it is known that at least one processor cannot receive the data, and the sender's processor outputs the same data again. At this time, the bus 24 is also set to "1" to indicate that data is being retransmitted. The processor then repeats data retransmission until the buses 25, 26, and 27 become (1, 0, 0). As a result, bus 2
This means that the same data has been sent to the processor having the processor number specified in step 2 or all the processors having the block number specified by bus 22. If the bus 27 becomes "1" during this process, it means that one of the receiving processors has detected a data error, and the sending processor may perform some kind of processing, such as data retransmission or diagnosis. Perform processing. Furthermore, during data transfer, bus 2
If 5 does not become "1", that is, if no processor responds, it means that a non-existent processor number or block number has been specified, and this is considered to be a program error. In this case, the software is notified accordingly. Next, the operation of the receiving processor will be explained. FIG. 2 shows the circuitry required for the receiving processor to respond. In the figure, 51 to 54 are registers for storing the processor number and block number of each processor, and the numbers are set via the signal line 40. Here, four registers 51 to 54
is used, but the number of these registers can be any number. Each processor 11-14 can have processor numbers and block numbers equal to the number of registers 51-54. In particular, broadcast transfer is possible for blocks that have the same block number among multiple processors. Address comparators 61 to 64 compare the programmer number or block number given from the sender's processor via the address bus 22 and the contents stored in the registers 51 to 54, and determine if any one of them matches. In this case, the output of the OR circuit 80 becomes "1". At this time, if the bus 23 is "1", that is, data is being transferred, the output of the AND circuit 81 becomes "1", indicating that another processor is about to send data to this processor. This output is output to the bus 25 via the gate 92 as a response signal. The flip-flop 45 indicates that data exists in the data buffer register 42. When this flip-flop 45 is "1", that is, when the buffer register is not yet empty, the AND circuit 8
When the output of 1 goes to ``1'', bus 26 goes to ``1'', indicating to the sender's processor that the data could not be received. Reference numeral 43 denotes an error detection circuit that performs a data validation check, and when an error is detected, the bus 27 is set to "1" via an AND circuit 85. The flip-flop 44 operates so that it becomes "1" when it receives data, and becomes "0" when it cannot receive data, that is, when the output of the AND circuit 84 becomes "1". The output of flip-flop 44 is input to NAND circuit 90 along with a signal on bus 24 indicating data retransmission. The output of this NAND circuit 90 becomes "0" when both the signals on the flip-flop 44 and the bus 24 are "1". That is, it becomes "0" when data has already been received during data retransmission, and operates to inhibit the clock signal of the buffer register 42 via the AND circuits 82 and 83. Further, the AND circuit 83 serves to inhibit the clock signal of the buffer register 42 via the inverter 91 when the output of the flip-flop 45 is "1", that is, when data still exists in the buffer register 42. also.
The clock signal to the buffer register 42 is such that the AND circuit 81 is "1", that is, data is sent to the processor, and the flip-flop 45 is 0, that is, there is no data in the buffer register 42.
Moreover, when the flip-flop 44 is 0, that is, the data has not been received yet, it becomes "1",
As a result, the contents of the data bus 21 are taken in. As described above, according to the system according to this embodiment, the registers 51 to 54 of the receiving processor
By simply storing a block number common to multiple processors to which the same data is transferred, the sending processor can freely transfer data in the same way it transfers data to a single processor. It becomes possible to perform broadcast transfer to the processor. Moreover, according to this embodiment, there is provided means for checking whether or not all specified processors have received data, and means for prohibiting data once received from being received again. It is possible to prevent the appearance of a processor that does not receive the same data or the appearance of a processor that receives the same data more than once, and data transfer can be ensured. Next, other embodiments of the present invention will be described. In this system, as shown in FIG.
04, and data is transferred on this loop. The format of transfer data in this system is as shown in FIG. 4, for example. That is, data is arranged in the DATA section 121, a processor number or block number is arranged in the PN section 122, and S0 and S1 sections 1
23 and 124 are arranged with the response information of the receiver's processor, the R section 125 is arranged with information indicating data retransmission, and the F section 126 is arranged with the response information of the receiver's processor.
1 contains information indicating that data exists. When the sender's processor attempts to send data, F="1", R="0", S1="1", S0="
It is set to "0", the processor number or block number is placed in the PN section, the data is placed in the DATA section, and this information is output to the adjacent processor. After that, S1,
The response information of S0 is monitored, and if (S1, S0) is (0, 0), it is determined that the data has been received correctly, and if (0, 1), it is determined that the data has been received correctly.
It is determined that some data could not be received, and F="1", R="1", S1="1", S0="0"
The same data is retransmitted as . When (S1, S0) returns as (1, 1), it is determined that one of the receiving processors has detected an error and performs error recovery processing. This operation of S1 and S0 can be realized with a simple logic circuit. A circuit for the receiving processor to respond is shown in FIG. In this circuit, the same parts as those shown in the previous embodiment are given the same reference numerals, and the explanation of the overlapping parts will be omitted. In this circuit, the bus 23 in FIG.
The bus 24 corresponds to the R section 125, the bus 22 corresponds to the PN section 122, and the bus 21 corresponds to the DATA section 121. The roles of buses 25, 26, and 27 in FIG. 2 are S1 section 124 and S0 section 1.
23, and in this point the operation is slightly different from the previous embodiment. In addition, 110 in the figure indicates S1,
This is a control circuit that operates on the S0 section, and outputs the output signal of the error detection circuit 43, the output of the flip-flop 45 that indicates whether the buffer register is empty, and the output of the AND gate 81 that indicates that data is being transmitted to this processor. The operation is as shown in the table below.

[Table] (S1, S0) basically transferred (1, 0)...data. (0,0)...Some processor received data. (0,1)...There was a processor that could not receive data. (1,1)...A processor detected an error. This means that the sender's processor sets the state to (1, 0). Remain in this state (S1,
If S0) returns to the sender's processor, it means that it did not respond to any processor. ~ in the above table... was not a transfer to that processor. ...The data was received correctly. ...Another processor had already detected the error. ...This processor detected an error. ...The processor received the data, but some other processors were unable to receive the data. ...The buffer was not empty and no data could be received. corresponds to each. The control circuit 110 in FIG. 5 generates S1 and S0 signals as shown in the above table. This control circuit 110 is also a simple combinational circuit, for example, PLA (Programmable Logic
This can be realized extremely easily using methods such as Array). [Effects of the Invention] As described above, according to the present invention, arbitrary processors in a parallel processing system are divided into groups specified by block numbers, each processor is provided with means for storing the block number, and The block number specified by the sender's processor is compared with the block number stored internally, and the data is accepted when the comparison results match. Broadcast transfer can be performed using the same procedure as one-to-one data transfer. Therefore, according to the present invention, in a large-scale parallel processing system, a plurality of programs can be distributed to a plurality of processors, and broadcast transfer can be freely performed within each program. I can make the whole thing work. Furthermore, even if the structure of a single program changes dynamically over time and the processors to which broadcast data should be transferred also change, this can be dealt with flexibly and the parallel processing system can be operated efficiently. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a parallel processing system according to an embodiment of the present invention, FIG. 2 is a more detailed circuit diagram of a processor in the same system, and FIG.
The figure is a block diagram showing the configuration of a parallel processing system according to another embodiment of the present invention, FIG. 4 is a diagram showing the format of transferred information in the same system, and FIG. 5 is a more detailed circuit diagram of the processor in the same system. , FIG. 6 is a diagram showing the general configuration of a parallel processing system,
FIG. 7 is a diagram showing a format of transferred data in the same system, FIG. 8 is a diagram showing an example of processor allocation in the same system, and FIG. 9 is a diagram showing an example of a program execution state in the same system. 11-14, 201-204, 311-319
...Processor, 21-27, 101-104...Bus, 51-54...Register, 61-64...Comparator.

Claims (1)

[Scope of Claims] 1. In a parallel processing system comprising a plurality of processors and a coupling means for coupling each two adjacent processors in a loop so that data can be transferred, each of the processors comprises: A block number storage means stores a block number that specifies a processor that receives common data during broadcast transfer, and the block number stored in this block number storage means is compared with the block number sent from the sender's processor. a comparison means for reading the data from the sender's processor when the comparison result of the comparison means matches, and a first state indicating that the data has been transferred;
means for transmitting, as 2-bit information, a second state indicating that one of the processors has received the data, and a third state indicating that there is a processor that has not received the data; The master processor has a means for transmitting the data, the block number of the destination, and 2-bit information in the first state, and a means for transmitting the data, the block number of the destination, and the specified 2-bit information when the 2-bit information received via another processor is in the second state. means for determining that all the processors that have stored the specified block number have received the data; and when the received 2-bit information is in a third state, even one of the processors that has stored the specified block number; means for determining that there is data that could not be received and retransmitting the same data, and the receiving processor among the processors determines whether or not to receive the data if the comparison result of the comparing means is a match. If the data can be received, it receives the data, and if the received 2-bit information is in the first state, it changes to the second state, and if it is in the second or third state, it remains as it is. The means to send it, and if it cannot be received, the information received 2
A parallel processing system characterized by comprising: means for changing bit information to a third state when it is in the first state or the second state, and transmitting the bit information as is when it is in the third state.