JPS55135925A - Information transfer device - Google Patents

Information transfer device

Info

Publication number
JPS55135925A
JPS55135925A JP4278779A JP4278779A JPS55135925A JP S55135925 A JPS55135925 A JP S55135925A JP 4278779 A JP4278779 A JP 4278779A JP 4278779 A JP4278779 A JP 4278779A JP S55135925 A JPS55135925 A JP S55135925A
Authority
JP
Japan
Prior art keywords
response
signal line
contents
sending
receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4278779A
Other languages
Japanese (ja)
Other versions
JPS6155140B2 (en
Inventor
Takemi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4278779A priority Critical patent/JPS55135925A/en
Publication of JPS55135925A publication Critical patent/JPS55135925A/en
Publication of JPS6155140B2 publication Critical patent/JPS6155140B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to confirm that all the sending and receiving circuits have received information, by setting all the response circuits in order that the response signal lines can be a high level, in numbers of unspecified transmission object information processing devices.
CONSTITUTION: When a status signal line 105 has become a low level, a comparator 11 of the receiving part 10B energizes a selective signal line 111 and opens a receiving data gate 14 to the internal data bus, in case the contents of the status bus 102 and those of the status register 24 have been matched. And in case a sending signal line 103 has become a low level, so far as contents of the register 24 are not conforming, a non-selective response control line 112 is energized and the response circuit 13 is set. In case contents of the register 24 are matched, a confirmation response circuit 15 energizes a write-in line 204, is made to write in contents of the bus 201, and simultaneously sets a circuit 13, only when both the signal line 111 and the ready line 203 have been energized. When all the circuits 13 have been set in such a way as mentioned hereinabove, the response signal line 104 becomes a high level finally, and the sending part is informed that all the sending and receiving circuits have completed receiving a signal.
COPYRIGHT: (C)1980,JPO&Japio
JP4278779A 1979-04-09 1979-04-09 Information transfer device Granted JPS55135925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4278779A JPS55135925A (en) 1979-04-09 1979-04-09 Information transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4278779A JPS55135925A (en) 1979-04-09 1979-04-09 Information transfer device

Publications (2)

Publication Number Publication Date
JPS55135925A true JPS55135925A (en) 1980-10-23
JPS6155140B2 JPS6155140B2 (en) 1986-11-26

Family

ID=12645667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4278779A Granted JPS55135925A (en) 1979-04-09 1979-04-09 Information transfer device

Country Status (1)

Country Link
JP (1) JPS55135925A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63228363A (en) * 1987-03-02 1988-09-22 フォース コンピュータース ゲーエムベーハー Method of operating computer system and multiple processor system using the same
JPS6462759A (en) * 1987-09-03 1989-03-09 Agency Ind Science Techn Parallel processing system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63228363A (en) * 1987-03-02 1988-09-22 フォース コンピュータース ゲーエムベーハー Method of operating computer system and multiple processor system using the same
JPS6462759A (en) * 1987-09-03 1989-03-09 Agency Ind Science Techn Parallel processing system
JPH0520783B2 (en) * 1987-09-03 1993-03-22 Kogyo Gijutsuin

Also Published As

Publication number Publication date
JPS6155140B2 (en) 1986-11-26

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