JPS57137917A - Error information transfer system - Google Patents

Error information transfer system

Info

Publication number
JPS57137917A
JPS57137917A JP56023795A JP2379581A JPS57137917A JP S57137917 A JPS57137917 A JP S57137917A JP 56023795 A JP56023795 A JP 56023795A JP 2379581 A JP2379581 A JP 2379581A JP S57137917 A JPS57137917 A JP S57137917A
Authority
JP
Japan
Prior art keywords
information
error
peripheral equipment
circuit
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56023795A
Other languages
Japanese (ja)
Inventor
Masao Sato
Teruyoshi Mita
Fumio Hoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56023795A priority Critical patent/JPS57137917A/en
Publication of JPS57137917A publication Critical patent/JPS57137917A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To use conventional interface control as it is without providing an additional wiring, by transferring error information by an information bus for sending and receiving information between a storage device and a peripheral equipment. CONSTITUTION:Error information is transferred by use of an information bus used for transferring data information between a storage device and a peripheral equipment. For instance, in case when an error is not detected in a read error information detecting circuit 1, information passes through AND circuits 8-0- 8-15 from the storage device 7 and is inputted to the peripheral equipment 3 through a bus line 4. Subsequently, in case when an error is detected in the read information, a detection error signal is sent out to AND circuits 10-0-10-2 and an OR circuit 11 by the error detecting circuit, and the polarity of terminals A, B of a controlling circuit 5 is converted to ''0'' and ''1'', respectively, by an output signal from the OR circuit 11. After that, the error detecting signal is entered into between the ''0'' bit and the second bit of the respective data buses, and the error information is sent out to the peripheral equipment 3.
JP56023795A 1981-02-20 1981-02-20 Error information transfer system Pending JPS57137917A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56023795A JPS57137917A (en) 1981-02-20 1981-02-20 Error information transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56023795A JPS57137917A (en) 1981-02-20 1981-02-20 Error information transfer system

Publications (1)

Publication Number Publication Date
JPS57137917A true JPS57137917A (en) 1982-08-25

Family

ID=12120252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56023795A Pending JPS57137917A (en) 1981-02-20 1981-02-20 Error information transfer system

Country Status (1)

Country Link
JP (1) JPS57137917A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60207986A (en) * 1984-04-02 1985-10-19 Toshiba Corp Data processing system
JPS62245343A (en) * 1986-04-18 1987-10-26 Hitachi Ltd Failure diagnosis display method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60207986A (en) * 1984-04-02 1985-10-19 Toshiba Corp Data processing system
JPS62245343A (en) * 1986-04-18 1987-10-26 Hitachi Ltd Failure diagnosis display method

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