JPS5676826A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS5676826A
JPS5676826A JP15543579A JP15543579A JPS5676826A JP S5676826 A JPS5676826 A JP S5676826A JP 15543579 A JP15543579 A JP 15543579A JP 15543579 A JP15543579 A JP 15543579A JP S5676826 A JPS5676826 A JP S5676826A
Authority
JP
Japan
Prior art keywords
address
data transfer
bus
sent
cpu1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15543579A
Other languages
Japanese (ja)
Inventor
Takehiko Tokura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15543579A priority Critical patent/JPS5676826A/en
Publication of JPS5676826A publication Critical patent/JPS5676826A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To reduce the errors of the data transfer and thus increase the reliability of the data transfer, by giving comparison between the answer signal having the address sent from the remote device as its contents and the contents of the address sent by the self-device and then establishing the data transfer only when a coincidence is obtained through the above comparison.
CONSTITUTION: A connection is given among the CPU1 plus the input/output devices 3 and 4 via the address bus 1a, data bus 1b, control bus 1c and answer bus 1d each. Then the address of the device 3 of 4 is sent to the bus 1a from the CPU1. This address is then supplied to the detecting circit 5 of the devices 3 and 4 to be compared with the self-address of the device 3 or 4. In case a coincidence is obtained through the above comparison, the signal 5a is sent to the sending circuit 6. Then the self-address is sent to the CPU1 from the circuit 6 via the bus 1d. The answer signal sent from the bus 1d is detected by the detecting circuit 2 of the CPU1, and comparison is given between the answer signal and the transmitted address. And the data transfer is established when a coincidence is obtained through the above comparison. In such way, the errors are reduced for the data transfer, thus increasing the reliability of the data transfer.
COPYRIGHT: (C)1981,JPO&Japio
JP15543579A 1979-11-27 1979-11-27 Data transfer control system Pending JPS5676826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15543579A JPS5676826A (en) 1979-11-27 1979-11-27 Data transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15543579A JPS5676826A (en) 1979-11-27 1979-11-27 Data transfer control system

Publications (1)

Publication Number Publication Date
JPS5676826A true JPS5676826A (en) 1981-06-24

Family

ID=15605956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15543579A Pending JPS5676826A (en) 1979-11-27 1979-11-27 Data transfer control system

Country Status (1)

Country Link
JP (1) JPS5676826A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61165170A (en) * 1984-12-19 1986-07-25 Fujitsu Ltd Bus controlling system
JPS62226263A (en) * 1986-03-27 1987-10-05 Nec Corp Multiprocessor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61165170A (en) * 1984-12-19 1986-07-25 Fujitsu Ltd Bus controlling system
JPH0238968B2 (en) * 1984-12-19 1990-09-03 Fujitsu Ltd
JPS62226263A (en) * 1986-03-27 1987-10-05 Nec Corp Multiprocessor device

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