JPS62226263A - Multiprocessor device - Google Patents

Abstract

PURPOSE:To enable a spare processor to perform a call via a processor bus regardless of a working processor even with a process having a double structure, by selecting those processors independently of each other. CONSTITUTION:A system control processor SP carries out the diagnosis of a fault by sending the processor number and the information on the selecting conditions of the called side and the transfer information to a processor bus. These information are sent to a processor bus interface PBI via the processor bus. Each PBI collates the received processor number with its own processor number and performs the incoming processing as long as side collation is successful. Thus the processor SP can choose an optional local processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a load-balancing and function-distributing multiprocessor device connected to a processor bus.

[Conventional technology]

According to a conventional multiprocessor system, a load-balanced single-configuration processor and a function-distributed dual-configuration processor are connected to a processor bus, and each processor has a single processor number regardless of whether it is in a single- or duplex configuration. The processor bus interface device of the backup processor in the redundant configuration was configured to operate in a blocked state.

[Problem that the invention seeks to solve]

As mentioned above, even if a conventional multiprocessor system has a duplex configuration, the processor bus interface device of the standby processor is configured to operate in a blocked state. When diagnosing a fault, the redundant backup processor has the disadvantage that it cannot communicate at all via the processor bus.

[Means for solving problems]

In order to solve these problems, the present invention connects a plurality of processors to a processor bus through a processor bus interface, and each processor is given a unique processor number. .

[For production]

The selected processor exchanges data with the processor bus via the processor bus interface.

〔Example〕

FIG. 1 is a block diagram of an apparatus showing an embodiment of the present invention. In the figure, the functions and configuration of each processor are as follows. The local processor LP is a load and function distributed type processor that is configured to detect changes in the state of lines and trunks and request the higher-level processor to change the connection state. It will be done. The main processor MP is a load-balanced processor that performs a series of state transition sequence processes based on requests from the local processor LP.
Built into the system with +1 redundancy configuration. The time division switch processor TP is a functionally distributed type processor that controls the time division switch according to instructions from the main processor MP, and is incorporated into the system in a working/standby duplex configuration.

The system management processor SP is a functionally distributed processor that manages the entire system and controls the man-machine interface, and is incorporated into the system in a dual configuration of active/backup. Each processor, that is, the active/spare processor, is assigned a unique processor number, and the processor bus interface device FB
When I obtains exclusive rights to the processor bus during outgoing processing, it sends the called side processor number, called side selection condition information, and transfer information, and when it detects an incoming call during incoming processing. The called processor number from the calling processor is compared with the own processor number, and when a match is made, data can be transferred between the processor and the processor bus. In addition, the processor bus interface FBI has a means for returning whether or not information transfer is possible to the calling processor based on the callee selection condition information and the state of the own processor. call processor optionally,
In other words, the configuration is such that it is possible to select even the standby processor in the duplex configuration. The system management processor SP has the operational management function for the entire system, and periodically checks the operation of all processors, and if a failure occurs in the active processor in a redundant configuration, it switches to the standby processor. When diagnosing a faulty processor later, a diagnosis instruction is sent to the standby processor via the processor bus. Note that TDSW is a time division switch,
IOC is I10 controller, MAT is maintenance terminal, BS
C is a processor bus control device.

Since this apparatus is configured as described above, when the system management processor SP performs a fault diagnosis, it sends the called side processor number, called side selection condition information, and transfer information to the processor bus.

This information is passed through the processor bus to the processor server processor bus interface FBI, which compares the sent processor number with its own processor number, and the one that is successfully matched processes the incoming call. In this way, the system management processor SP can select any local processor.

〔Effect of the invention〕

As explained above, in this invention, each processor is selected individually, so even if the processor has a dual configuration, the standby processor is connected to the processor bus interface, and the processor bus is connected to the processor bus interface regardless of the active system. This has the effect of allowing telephone calls to be made via the .

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. LP...Local processor, MP...
...Main processor, TP...Time division switch processor, SP...System management processor, FBI...Processor bus interface device, R8C...Processor bus interface device (Sutsukuda 1 Xiang Magazine TT) IC0W,,. ...Time division switch, IOC...110
Controller, MAT... Maintenance terminal.

Claims (1)

[Claims] In a multiprocessor device consisting of a plurality of processors connected to a processor bus, a processor bus interface is provided between each processor and the processor bus, and this processor bus interface communicates the processor number and its processor supplied via the processor bus. 1. A multiprocessor device, characterized in that the multiprocessor device is configured to start transferring data between its own processor and a processor bus when a bus interface matches the processor number of a connected processor.