KR930008708B1 - Low level control system of electronic exchange - Google Patents

Abstract

A low-level controlling apparatus for TDX has a first processor including a first peripheral processor common board connected to an inter-processor communication unit via a unit link, a first peripheral processor interface board and a second peripheral processor interface board, and a second processor including a second peripheral processor common board, a third peripheral processor interface board and a fourth peripheral processor interface board. The hardware units are controlled in normal operation by a load sharing system, and one normal processor controls overall hardware units to treat overall load when the other processor fails, thereby improving reliability.

Description

Low level control device of electronic changer

1 is a conceptual diagram of a TDX-10 low-level control structure.

2 is a block diagram of the present invention.

3 is an interprocessor status signal monitor of the present invention.

* Explanation of symbols for main parts of the drawings

TD bus: Telephony device control bus PP: Peripheral processor

PPCA: Peripheral Processor Common Board PPIA: Peripheral Processor Interface

PPS bus: Peripheral processor system bus U-Link: Unit link

IPC: Inter Processor Communication INOD: IPC Node

PPDownout: When the PP function fails, Pair: Signal that informs the processor status to the processor

PPDownin: Signal received status from partner processor when failing PP function fail

TB-Selout: Signal that informs the TD-bus of the other processor of the status of its own TD-bus

TB-Selin: Signal receiving the status of the partner TD-bus from the partner processor's TD-bus

The present invention relates to a low-level control device of an electronic switch.

In general, the low-level control structure of the electronic switchboard is an active / stand-by redundancy configuration or a single control structure, which has low flexibility to cope with the load of the system and has a single control. Rescue affects the reliability of the system.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its purpose is to be widely used for low level control of an electronic exchanger.

The present invention includes a first processor (A) and a second processor (B) for high level control in order to achieve the above object, but controls the hardware unit in the form of load sharing through the control bus during normal operation and fail of the state processor In the event of a failure, the healthy processor is configured to collectively control the hardware unit to handle the entire load.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 to 3 illustrate the structural diagram of the present invention, in particular, applied to the TDX-10 electron exchanger. FIG. 1 is a conceptual diagram of a TDX-10 lower level control structure, and FIG. 2 is a schematic diagram of the present invention. 3 is an interprocessor status signal monitoring diagram of the present invention.

In the figure, the TD-bus is the tallyphone device control bus, the PPCA is the peripheral processor common board, the PP is the peripheral processor, the PPIA is the peripheral processor interface board, the PPS bus is the peripheral processor system bus, and the U-Link is the unit link. IPC is the inter-processor communication, INOD is the IPC node, PPDownout is the signal that informs the processor status to the partner processor when the PP function fails, and PPDownin is the signal that receives the status from the partner processor when the PP function fails. The TB-Selout indicates a signal indicating the state of its own TD-bus to the counterpart TD-bus, and the TB-Selim indicates a signal receiving the state of the counterpart TD-bus from the counterpart TD-bus.

As shown in FIG. 1, a low-level control structure is used for load sharing while Processor A and Processor B perform their respective jobs during normal operation. It works in the form In addition, the control scheme (Scheme) is a structure that can be configured in a redundant configuration of Active / Standby (Software), but in the TDX-10 is controlled by a load sharing scheme (Scheme).

Referring next to FIG. 2, processor A and processor B are each connected to an INOD to communicate with a high-level processor, and processor A and processor B, respectively, are assigned to load sharing. It works in the form In normal operation, the load sharing type of operation is performed by the processor A through the TD bus A (0A) and the TD bus A (1A), respectively, in hardware unit 0 (H / W unit 0) and hardware unit 2 (H / W unit 2). Processor B controls hardware unit 1 (H / W unit 1) and hardware unit 3 (H / W unit 3) via TD bus B (0B) and TD bus B (1B), respectively. . Active / Stand-by redundancy configuration means that if processor A is active, processor B is standby and processor A is TD-bus A (0A, 0B, 1A, 1B) Control all hardware units 0, 1, 2, 3 (H / W units 0, 1, 2, 3), and if processor A is standby and processor B is active, then processor B is TD-Bus (0A, The hardware units 0, 1, 2 and 3 (H / W units 0, 1, 2 and 3) are all controlled via 0B, 1A and 1B. In order to enable a load sharing type and an active / standby redundancy configuration, the processor A and the processor B are configured to monitor the status of the mutual processor as shown in the third diagram. It is also configured to allow change-over of TD-bus). As shown in FIG. 3EH, PPDownout, which is one of the status signals of the mutual processors, is a signal informing the counterpart processor of a function failure of the processor and is received as the PPDownin in the counterpart processor. In addition, to carry over the bus (TD-bus), the state of the bus (TB-bus) is informed to the port of the counterpart bus (TD-bus) to TB-Selout, and also to the partner bus (Pair TB-bus). Received the status of TD-Selin.

As described above, in the present invention, the low-level control of the all-electronic exchange is configured in a redundant configuration or a load sharing form of active / standby, and operates in a load sharing form in normal operation to increase flexibility of the system to increase the flexibility of the load. Can cope with the increase and increase the reliability of the system.

Claims (3)

The first peripheral processor common board (PPCA (A)) and the peripheral processor system bus (PPS bus) connected to the inter-processor communication unit (IPC unit) via a unit link (U-LINK) to communicate with the upper level processor. The first peripheral processor interface board (PPIA (0)) connected to the first peripheral processor common board and connected to the first and second hardware units HW0 and HW1 of the call path via a telephone device control bus (TD bus). And a second peripheral processor interface board connected to the first peripheral processor common board through the peripheral processor system bus and connected to the third and fourth hardware units HW2 and HW3 of a call path through a telephone device control bus. A first processor means A composed of (PPIA (1)) and a second peripheral processor common board connected to the inter-processor communication unit (IPC unit) via a unit link (U-LINK) PPCA (B)), a peripheral processor system bus (PPS bus) connected to the second peripheral processor common board and a telephone device control bus (TD bus) through the first and second hardware units (HW3, HW4) A third peripheral processor interface board (PPIA (0)) coupled to the second peripheral processor common board via the peripheral processor system bus and the third and fourth hardware units (HW2) via a telephone device control bus. And a second processor means (B) composed of a fourth peripheral processor interface board (PPIA (1)) connected to HW3, controlling the hardware units in the form of load sharing during normal operation, and failing of one processor means. In the event of a failure, the normal processor side controls the hardware units collectively to handle the entire load. High level control. The method according to claim 1, wherein the first processor means (A) and the second processor means (B) not only monitor the status signals of the other processor means, but also the redundant telephone control bus (TD BUS). Low-level control of an electronic switch, characterized in that it is configured to monitor the state of the state bus so as to be change-over. The method of claim 1, wherein the first processor means (A) and the second processor means (B) are each active / stand-by redundant type via a telephone device control bus (TD-BUS). Low level control device for an electronic switchboard, characterized in that configured to control a hardware unit.

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