JPS54126436A - Additional processing unit connection system - Google Patents

Additional processing unit connection system

Info

Publication number
JPS54126436A
JPS54126436A JP3433278A JP3433278A JPS54126436A JP S54126436 A JPS54126436 A JP S54126436A JP 3433278 A JP3433278 A JP 3433278A JP 3433278 A JP3433278 A JP 3433278A JP S54126436 A JPS54126436 A JP S54126436A
Authority
JP
Japan
Prior art keywords
unit
cpu
additional processing
bus
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3433278A
Other languages
Japanese (ja)
Inventor
Hiroshi Motokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3433278A priority Critical patent/JPS54126436A/en
Publication of JPS54126436A publication Critical patent/JPS54126436A/en
Pending legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To make it possible to connect logically a CPU and an additional processing unit by switching, by providing a means to store the unit number and a means to compare the unit number in the system where the CPU and the additional processing unit are connected by a single bus.
CONSTITUTION: Memory units 1, CPUs 2 and 3, and additional processing units 4 and 5 are connected by single bus 101. In units 3 and 5, values of channel number setting switches 7 are so set that they may be different from each other, and are stored in memory circuits 6. When fetching and decoding an instruction from memory unit 1, CPU 2 transmits the channel number, which is given to unit 4, through the address information line of bus 101. When the number set by switch 7 of unit 4 and the number given from bus 101 agree with each other, a coincidence signal is issued from comparator circuit 8 to select unit 4. Then, CPU 2 transmits the channel number and a channel switching command having disconnection information to unit 4 to disconnect unit 4, and next, a channel switching command having connection information is outputted to unit 5 to connect the CPU and unit 5.
COPYRIGHT: (C)1979,JPO&Japio
JP3433278A 1978-03-24 1978-03-24 Additional processing unit connection system Pending JPS54126436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3433278A JPS54126436A (en) 1978-03-24 1978-03-24 Additional processing unit connection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3433278A JPS54126436A (en) 1978-03-24 1978-03-24 Additional processing unit connection system

Publications (1)

Publication Number Publication Date
JPS54126436A true JPS54126436A (en) 1979-10-01

Family

ID=12411181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3433278A Pending JPS54126436A (en) 1978-03-24 1978-03-24 Additional processing unit connection system

Country Status (1)

Country Link
JP (1) JPS54126436A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021692A (en) * 1983-07-15 1985-02-04 Matsushita Electric Works Ltd Multiplex transmission system
JPS6174144U (en) * 1980-07-30 1986-05-20
JPS62226263A (en) * 1986-03-27 1987-10-05 Nec Corp Multiprocessor device
JPS63157238A (en) * 1986-12-22 1988-06-30 Fuji Electric Co Ltd Computer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6174144U (en) * 1980-07-30 1986-05-20
JPS6021692A (en) * 1983-07-15 1985-02-04 Matsushita Electric Works Ltd Multiplex transmission system
JPH0342757B2 (en) * 1983-07-15 1991-06-28
JPS62226263A (en) * 1986-03-27 1987-10-05 Nec Corp Multiprocessor device
JPS63157238A (en) * 1986-12-22 1988-06-30 Fuji Electric Co Ltd Computer

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