JPS55121555A - Program control system - Google Patents

Program control system

Info

Publication number
JPS55121555A
JPS55121555A JP2953179A JP2953179A JPS55121555A JP S55121555 A JPS55121555 A JP S55121555A JP 2953179 A JP2953179 A JP 2953179A JP 2953179 A JP2953179 A JP 2953179A JP S55121555 A JPS55121555 A JP S55121555A
Authority
JP
Japan
Prior art keywords
memory
data
content
cpu
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2953179A
Other languages
Japanese (ja)
Inventor
Takayoshi Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2953179A priority Critical patent/JPS55121555A/en
Publication of JPS55121555A publication Critical patent/JPS55121555A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To provide program development with efficiency by sending the preset content of a specific register to CPU as if it were the memory content, without reference to the memory content when reading data at a specific address on the memory.
CONSTITUTION: In breakpoint setting resister BPR, data concerned with a desired address is set depending upon an instruction. Comparing circuit CMP, connected to BPR and address ADB, compares the data set in BPR with address signals transferred via ADB one after another and when the both agree with each other, a coincidence signal is generated to set control FF (CFF). Register PGR is stored with data to be transferred to CPU instead of a memory. Then, CFF when set through the switching of sultiplexer MPX sends the content of PGR to CPU via MPX, but when it is reset through the operation of switch S, it sends memory data in main memory unit MM to CPU via MPX.
COPYRIGHT: (C)1980,JPO&Japio
JP2953179A 1979-03-13 1979-03-13 Program control system Pending JPS55121555A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2953179A JPS55121555A (en) 1979-03-13 1979-03-13 Program control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2953179A JPS55121555A (en) 1979-03-13 1979-03-13 Program control system

Publications (1)

Publication Number Publication Date
JPS55121555A true JPS55121555A (en) 1980-09-18

Family

ID=12278685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2953179A Pending JPS55121555A (en) 1979-03-13 1979-03-13 Program control system

Country Status (1)

Country Link
JP (1) JPS55121555A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197553A (en) * 1982-05-12 1983-11-17 Mitsubishi Electric Corp Program monitor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197553A (en) * 1982-05-12 1983-11-17 Mitsubishi Electric Corp Program monitor

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