JPS5629724A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5629724A
JPS5629724A JP10423279A JP10423279A JPS5629724A JP S5629724 A JPS5629724 A JP S5629724A JP 10423279 A JP10423279 A JP 10423279A JP 10423279 A JP10423279 A JP 10423279A JP S5629724 A JPS5629724 A JP S5629724A
Authority
JP
Japan
Prior art keywords
cpu10
power supply
rom11
data
fet9
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10423279A
Other languages
Japanese (ja)
Inventor
Takao Kamiriyou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10423279A priority Critical patent/JPS5629724A/en
Publication of JPS5629724A publication Critical patent/JPS5629724A/en
Pending legal-status Critical Current

Links

Landscapes

  • Direct Current Feeding And Distribution (AREA)
  • Power Sources (AREA)

Abstract

PURPOSE: To secure the holding of the data with the low power consumption and with no increment of the number of terminals, by having such a sonstitution in that the power supply is stopped to both the CPU and the memory part by opening the switch when the CPU completes the program process.
CONSTITUTION: When the CPU10 starts the operation, the operation start signal is supplied to the FF8 through the external terminal 6. And then the FET9 is closed to supply the power to both the CPU10 and the ROM11. When the CPU10 completes its operation, the reset signal 13 is generated within the CPU10 for the FF8. And the FET9 is cut off by the reset of the FF8 to stop the power supply to the CPU10 and the ROM11. On the other hand, the power supply is still continued to the RAM12 at this moment, and thus the data can be held even with the voltage of a low level. In case the interruption control signal 6 is supplied from outside at this moment, the FF8 is set to start again the power supply to the CPU10 and the ROM11. Thus the CPU10 is actuated. In such way, the data of the RAM12 can be held even with the voltage of a low level and without providing two units of the power supply terminal which are so far required.
COPYRIGHT: (C)1981,JPO&Japio
JP10423279A 1979-08-15 1979-08-15 Information processor Pending JPS5629724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10423279A JPS5629724A (en) 1979-08-15 1979-08-15 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10423279A JPS5629724A (en) 1979-08-15 1979-08-15 Information processor

Publications (1)

Publication Number Publication Date
JPS5629724A true JPS5629724A (en) 1981-03-25

Family

ID=14375208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10423279A Pending JPS5629724A (en) 1979-08-15 1979-08-15 Information processor

Country Status (1)

Country Link
JP (1) JPS5629724A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5858625A (en) * 1981-09-30 1983-04-07 Matsushita Electric Ind Co Ltd Electric power saving electronic apparatus
JPS5957315A (en) * 1982-09-27 1984-04-02 Nec Corp Control system of processing request signal
JPS59220574A (en) * 1983-05-31 1984-12-12 松下電工株式会社 Cpu speeding preventing system in electronic lock system
JPS62103766A (en) * 1985-10-30 1987-05-14 Omron Tateisi Electronics Co Card certifying terminal device
JPH01173897U (en) * 1988-05-13 1989-12-11

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940838A (en) * 1972-08-25 1974-04-17

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940838A (en) * 1972-08-25 1974-04-17

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5858625A (en) * 1981-09-30 1983-04-07 Matsushita Electric Ind Co Ltd Electric power saving electronic apparatus
JPS5957315A (en) * 1982-09-27 1984-04-02 Nec Corp Control system of processing request signal
JPS59220574A (en) * 1983-05-31 1984-12-12 松下電工株式会社 Cpu speeding preventing system in electronic lock system
JPS62103766A (en) * 1985-10-30 1987-05-14 Omron Tateisi Electronics Co Card certifying terminal device
JPH01173897U (en) * 1988-05-13 1989-12-11

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