JPS5957315A - Control system of processing request signal - Google Patents

Control system of processing request signal

Info

Publication number
JPS5957315A
JPS5957315A JP57168983A JP16898382A JPS5957315A JP S5957315 A JPS5957315 A JP S5957315A JP 57168983 A JP57168983 A JP 57168983A JP 16898382 A JP16898382 A JP 16898382A JP S5957315 A JPS5957315 A JP S5957315A
Authority
JP
Japan
Prior art keywords
processing request
signal
computer
processing
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57168983A
Other languages
Japanese (ja)
Inventor
Kazuhide Noguchi
一秀 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57168983A priority Critical patent/JPS5957315A/en
Publication of JPS5957315A publication Critical patent/JPS5957315A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

PURPOSE:To prevent loss of processing by stopping a power supply control section, even if a new request exists for a prescribed time after the processing of a processing request signal of a computer is finished and the power supply is turned off, in a device using the power strobe control system. CONSTITUTION:When a processing request signal a1 is inputted to a processing request inhibit section 1 and a computer 2, the processing request inhibit section 1 outputs a power supply ON command signal (c), and the computer 2 processes the processing request signal a1. When the processing is finished, the computer 2 outputs a processing request clear signal b1 and the signal a1 is cleared. Then, a processing request inhibit signal (e) is transmitted to the processing request inhibit section 1 to inhibit the transmission of the power supply ON command signal (c) with a new processing request signal a2. A processing end signal (f) is transmitted to a power supply control section 3 in this state and a computer power strobe power supply signal (d) applied to itself is turned off.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明番よ、低消費電力化が要求ざれるコンピュータ装
置に関する。特に、その電源を間欠的に動作させるごと
によって低消費電力ＩＬを実現ずる制御（以下「パワー
スＩ・ローブ制御」という。）方式の装置に、この制御
に非同期でコンピュータに入力される処理要求に対し、
処理抜けをおこすことなく確実に処理を実行させる方式
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a computer device that requires low power consumption. In particular, for devices that use a control system that achieves low power IL consumption by intermittently operating the power supply (hereinafter referred to as "powers I lobe control"), processing requests that are input to the computer asynchronously to this control are applied. On the other hand,
The present invention relates to a method for reliably executing processing without causing processing omissions.

〔従来技術の説明〕[Description of prior art]

従来のこの種の装置はコンピュータでの処理が終了する
と、コンピュータは他の処理要求信号が入力されている
かどうかをチェックし、そのチェックした時点で処理要
求信号がなければ処理終了信号を電源制御部に送出して
自ら電源をオフにしていた。しかし、処理終了信号をコ
ンピュータが電源制御部に出力したタイミングと偶然に
極めて近い時間に他の処理要求信号が電源制御部に入力
されたとすると、重囲制御８１１部には処理要求信号か
ら作られる電源のオン指令信号と、処理終了信号ずなわ
らオフ指令信号とが同時に入力されることになり、誤動
作の原因となっていた。In conventional devices of this type, when processing is completed by the computer, the computer checks whether another processing request signal has been input, and if there is no processing request signal at the time of checking, the processing end signal is sent to the power supply control unit. and then turned off the power itself. However, if by chance another processing request signal is input to the power supply control section at a time very close to the timing at which the computer outputs the processing end signal to the power supply control section, the overlapping control section 811 receives a signal generated from the processing request signal. The power on command signal and the processing end signal as well as the off command signal are input at the same time, causing malfunctions.

また、これを防止するためにはあらゆるタイミングでオ
ン指令信号とオフ指令信号が重なった場合についてオン
１行令信号を有効とし、オフ指令信号を無効とし、かつ
そのときに電源の瞬断が発生しないようにする複雑なハ
ードウェアが必要であった。In addition, in order to prevent this, if the ON command signal and OFF command signal overlap at any timing, the ON 1 command signal is enabled and the OFF command signal is disabled, and at that time, a momentary power interruption occurs. Complex hardware was required to avoid this.

〔発明の目的〕[Purpose of the invention]

本発明はこの欠点を改良するもので、処理要求インヒビ
ソト部を設けて電源のオン指令信号とオフ指令信号とが
車なっても誤動作を防止することができる処理方式を提
供することを目的とする。The present invention aims to improve this drawback, and aims to provide a processing method that can prevent malfunctions even if the power on command signal and power off command signal are different by providing a processing request inhibiting section. .

〔発明の要点〕[Key points of the invention]

本発明は、：１ンビユータと、このコンピュータの電源
をオンオフ制御する電源制御部とを備え、この電源制御
ａ１１は、」二記二１ンビブーータに処理要求信号があ
るときは」１記コンピュータに電源が与えられ、−り記
コンピュータに処理要求信号がないときには上記−Ｉン
ピュータに電源を与えないように制御される処理要求信
号制御方式におい−（、十記二１ンピュータが処理要求
信号の処理を終了し”（−に配電源制御部で電源がオフ
にされてから一定時間は新たな処理要求信号があっても
上記電源制御部を停止させるよ・うに制御する手段を備
えたことを特徴とする。The present invention includes: (1) a computer, and a power control section that controls the power supply of this computer on and off; In the processing request signal control method in which power is not supplied to the above-mentioned computer when there is no processing request signal to the computer, the computer does not process the processing request signal. The apparatus is characterized by comprising means for controlling the power supply control unit to stop even if there is a new processing request signal for a certain period of time after the power supply is turned off by the distribution power supply control unit. do.

〔実施例による説明〕[Explanation based on examples]

本発明の一実施例を図面に基づいて説明する。 An embodiment of the present invention will be described based on the drawings.

第１図は、本発明−実施例の要部ゾし１ツク構成図であ
る。処理要求信号ａ１〜ａｎを処理要求インヒビソｔ・
ａｔ日およびコンピュータ２にそれぞれ導く。この処理
要求インヒビソト部１からの電源オン指令信号Ｃを電源
制御部３に導く。この電源制御部３にご１ンビユ一タ用
電源部４の出力を導く。FIG. 1 is a one-step configuration diagram showing the essential parts of an embodiment of the present invention. The processing request signals a1 to an are processed by a processing request inhibiter t.
at day and computer 2 respectively. The power-on command signal C from the processing request inhibiting section 1 is guided to the power supply control section 3. The output of the computer power supply section 4 is guided to this power supply control section 3.

また、電源制御ｇ１３３のコンピュータパワーストロー
ブ電源信号ｄを」１記コンピュータ２に導き、ごのコン
ピュータ２から処理要求クリア信号ｂ１〜ｔ）ｎを各装
置ｉ！７（図外）に導くとともに、処理要求インヒビソ
ト信号ｅを−Ｉ−記処理要求インヒビソト部１に導き、
処理終了４８号ｆを電源制御部３に導く。In addition, the computer power strobe power signal d of the power supply control g133 is guided to the computer 2, and the processing request clear signals b1 to t)n are sent from the computer 2 to each device i! 7 (not shown), and guides the processing request inhibiting signal e to the processing request inhibiting unit 1 described in -I-;
Processing completed No. 48f is guided to the power supply control section 3.

第２図は、第１し１に×印で示した点の信号波形を示す
動作タイムチ中−トである。第２図でＩは処理要求信号
ａ１、ａ２が市ならなかった場合の動作タイムチャー１
・を示し、同図■は処理要求信号ａｌ、ａ２の発生タイ
ミングが重なった場合の動作タイムチャー１・を示ず。FIG. 2 is an operation time chart showing the signal waveforms at the points indicated by the crosses in the first and second rows. In FIG. 2, I is the operation time chart 1 when the processing request signals a1 and a2 are not valid.
(2) in the same figure does not show the operation time chart 1 (1) when the generation timings of the processing request signals al and a2 overlap.

このような回路構成で、処理要求ｔＳ号ａ１〜ａ　ｎに
より処理要求インヒビソト部１で電源オン指令信号Ｃが
作られて電源制御部３でコンピュータパワースＩ・ロー
プ電源信号（１が出力される。これにより、コンピュー
タ２が動作を開始し処理要求信号ａ１〜ａｎの処理を行
う。コンピュータ２は処理が終了すると処理要求クリア
信号ｂ１〜ｂｎを出力し、処理要求信号ａ１〜ａＱをク
リアする。With such a circuit configuration, the processing request inhibiting section 1 generates the power-on command signal C according to the processing requests tS numbers a1 to an, and the power supply control section 3 outputs the computer power signal I/rope power signal (1). As a result, the computer 2 starts operating and processes the processing request signals a1 to an.When the processing is completed, the computer 2 outputs the processing request clear signals b1 to bn and clears the processing request signals a1 to aQ.

次に、コンピュータ２は処理要求インヒビソ］・信号ｅ
を出力し、その次のステップで出力される：１ンヒュー
タハワースｌ−ｔ＋−ブ電源信号をオブ４るための処理
終了信号ｆと、新たに処理要求（ば号ａｌ〜ａ　ｎが処
理要求インヒビット部１に入力された場合それにより出
力される電源オフ指令信号Ｃとが市ならないように制御
される。Next, the computer 2 issues a processing request inhibit signal e.
is output, and in the next step, a processing end signal f is output to output the output power signal f, and a new processing request (signs al to a n are processed) is output. When inputted to the request inhibit section 1, the power off command signal C outputted thereby is controlled so as not to be inconsistent with the power off command signal C.

ずなわら、いま第２図１に示゛４゛よ・うに、処理要求
信号ａ１が処理要求インヒビノド部１およびＺｌンピュ
ーク２に入力する。ごれにより、処理要求インヒビソト
部１ば電源オンＩｎ令信号Ｃを出刃する。これにユリ、
電源制御部３はコンピュータ２にコンピュータパワース
トローブ電源信号ｄを送出し、コンピュータ２は処理要
求信号ａ１の処理を開始する。コンピュータ２４Ｊ処理
が終了すると処理要求クリア信号ｂ１を出力し、処理要
求信号ａ１をクリアする。次にごコンピュータ２４Ｊ処
理要求インヒビソト（Ｒ号ｅを処理要求インヒビット部
１に送出し、新たな処理要求信号ａ２が処理要求インヒ
ビソ（・部１に人力しても電源オン指令信号Ｃの送出を
禁止する。この状態で、処理終ｒ信ｔＪｆを電源制御部
３に送出し、自分自身へ供給されている：１ンビュータ
パワーストし＋−ブ電源信号ｄをＡフにする。Now, as shown in FIG. 2 (4), the processing request signal a1 is input to the processing request inhibiting section 1 and the Zl pump 2. Due to the dirt, the processing request inhibiting section 1 outputs the power-on command signal C. Yuri to this,
The power supply control unit 3 sends a computer power strobe power signal d to the computer 2, and the computer 2 starts processing the processing request signal a1. When the computer 24J completes the processing, it outputs a processing request clear signal b1 and clears the processing request signal a1. Next, the computer 24J sends a processing request inhibit signal (R) to the processing request inhibit section 1, and a new processing request signal a2 is sent to the processing request inhibit section 1. In this state, it sends the processing end signal tJf to the power supply control section 3, and turns the power supply signal d supplied to itself into A-off by powering up the controller.

ここで、第２図１１で示すように、この処理終了信号ｒ
を出力したター（ミングに車／Ｓるようにして処理要求
信号ａ２が処理要求インヒヒソト部１に人力すると、処
理要求・Ｃンヒビソト口ｌｉ　Ｉ　Ｉｔその直前に入力
され）こ処理要求インヒヒソト信；ｊｅによっテ・イン
ヒビソトのためのタイマが動作中でありごのインヒヒソ
１−が解除されない限り電源オンｔｌＴ令信号Ｃ番；Ｉ
出力されない。このタイマの時間ｔは処理終了信号ｒの
出力が完了する時間よりもしくなるように設定しておく
。このタイマがりＪれたとき、すなわちインヒビソトが
解除されたときに処理要求信号ａ２によって出力される
べき電源オン指令信号Ｃが出力され、処理終了信号ｆと
電源オン指令信号Ｃが市ろ′ることが防止され、誤動作
が防止される。このため、洩雑を防御回路は不要となり
単なるフリップフロップで構成できるので、バーＩ′ウ
ェアが著しく筒車化できる。Here, as shown in FIG. 2, the processing end signal r
When the processing request signal a2 is manually inputted to the processing request inhibit unit 1 by the terminal that outputs the processing request signal a2, the processing request signal a2 is inputted just before that. The timer for inhibit is operating and the power is turned on unless the inhibit 1- is released.
No output. The time t of this timer is set to be longer than the time when the output of the processing end signal r is completed. When this timer expires, that is, when the inhibit is released, the power-on command signal C that should be output by the processing request signal a2 is output, and the processing end signal f and the power-on command signal C are mutually exclusive. is prevented, and malfunctions are prevented. Therefore, a leakage protection circuit is not required and the circuit can be constructed with a simple flip-flop, so that the bar I' wear can be made into a clock wheel.

以上説明したように本発明によれば、二１ンビュータの
パワース］・ローブ制御における非同期で入力される処
理要求に対して処理抜ｔＪを防ＩＩ−するごとができ、
インタバルタイマ等Ｇこよる処理時間の割りふりおよび
処理時間の制限等を無くすることができ処理効率を向−
１−することができ、しかも：１ンビユータのパワース
ト１．Ｉ−ブ制御による消ｖ＆！電力を減少させること
ができる。As explained above, according to the present invention, it is possible to prevent processing omissions in response to asynchronously input processing requests in power lobe control of a computer.
Processing efficiency can be improved by eliminating processing time allocation and processing time limitations caused by interval timers, etc.
1-Can be done, and: 1-viewer's power strike 1. Erasing by I-bu control &! Power can be reduced.

特に、本発明は低消費電力が要求されるコンピュータに
おりる電源のパｌノーストＩ：］−ブ制御によってその
低消費電力化に有効である。In particular, the present invention is effective in reducing power consumption by controlling the power supply to a computer that requires low power consumption.

【図面の簡単な説明】[Brief explanation of drawings]

第１図ｔＪ本発明一実施例の要部ブロソク構成図。 第２回目第１図に×印で示した点の信号波形を示す動作
タイムチャ−１・。 １・・・処理要求インヒビソト部、２・・・コンピュー
タ、３・・・電源制御部、４・・く１ンピユ一タ川電源
部。FIG. 1 is a block diagram of main parts of an embodiment of the present invention. 2nd Time Operation time chart 1 showing the signal waveforms at the points marked with x marks in Figure 1. DESCRIPTION OF SYMBOLS 1...Processing request inhibiting section, 2...Computer, 3...Power supply control section, 4...K1P Yutakawa power supply section.

Claims (1)

【特許請求の範囲】[Claims] （１）　　コンピュータと、 このコンピュータの電源をオンオフ制御する電源制御部
と を備え、 この電源制御部ｔｊ、」１記コンピュータに処理要求信
号があるときは上記コンピュータに電源が与えられ、上
記コンピュータに処理要求信号がないときには」二記二
２ンピュータに電源を与えないように制御される 処理要求信号制御方式において、 上記コンピュータが処理要求信号の処理を終了して上記
電源制御部で電源がオフにされてから一定時間は新たな
処理要求信号があっても上記電源制御部を停止させるよ
うに制御する手段を備えたことを特徴とする 請求(1) A computer, and a power control section for controlling the power supply of the computer on and off, and the power supply control section tj, when there is a processing request signal to the computer described in 1 above, power is supplied to the computer; In the processing request signal control method in which power is not supplied to the computer when there is no processing request signal, the computer finishes processing the processing request signal and the power is turned off by the power control unit. A claim characterized in that the power control unit is controlled to stop the power supply control unit even if there is a new processing request signal for a certain period of time after the processing request signal is received.
JP57168983A 1982-09-27 1982-09-27 Control system of processing request signal Pending JPS5957315A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57168983A JPS5957315A (en) 1982-09-27 1982-09-27 Control system of processing request signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57168983A JPS5957315A (en) 1982-09-27 1982-09-27 Control system of processing request signal

Publications (1)

Publication Number Publication Date
JPS5957315A true JPS5957315A (en) 1984-04-02

Family

ID=15878173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57168983A Pending JPS5957315A (en) 1982-09-27 1982-09-27 Control system of processing request signal

Country Status (1)

Country Link
JP (1) JPS5957315A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5629724A (en) * 1979-08-15 1981-03-25 Nec Corp Information processor
JPS5738231B2 (en) * 1974-03-12 1982-08-14

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5738231B2 (en) * 1974-03-12 1982-08-14
JPS5629724A (en) * 1979-08-15 1981-03-25 Nec Corp Information processor

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