JPS6124353A - Peripheral controller for communication - Google Patents

Abstract

PURPOSE:To control the titled controller from devices except a host processor by controlling a clock signal into a CMOS communication controller to reduce power consumption than that of normal operation. CONSTITUTION:As for the setting of the stand-by mode at first, an output of a 2-input NOR circuit 17 is inactivated by activating a signal lines 24 for the setting of the standby mode by a command from the host processor 1. Then an output of a 2-input AND circuit 14 is inactivated independently of the state of a system clock signal line 8, no reception circuit control clock signal is given to a signal line 23 and no reception circuit control clock signal is fed into a CMOS communication controller. Then the stand-by mode is set. The stand-by mode is released when a flag pattern (01111110) is received by the CMOS communication controller 2 through a reception serial data line 6.

Description

[Detailed description of the invention] (Technical field) The present invention relates to a communication peripheral control device.

(Prior Art) Among communication peripheral control devices, those made using the 0M08 circuit are characterized by operating with low power consumption. In addition, in order to keep power consumption low, during the period when the device is not operating (idle period or standby period), the externally supplied power signal is stopped internally, which is necessary for operation. is called standby prayer mode.

Conventionally, communication peripheral devices using the 0M08 circuit have the above-mentioned standby mode, but the control method for setting and canceling it is based on commands from the host processor, and cannot be controlled from an external source other than the host processor. could not be controlled.

For example, there is currently no good control method for canceling standby mode in the 0M08 communication controller, which is one of the communication peripheral control devices, after reception preparation is completed and before actual reception operation begins. I haven't seen it suggested.

(Object of the Invention) An object of the present invention is to provide a communication peripheral control device that realizes standby mode control in the communication peripheral control device with lower power consumption.

(Structure of the Invention) In order to achieve this object, the present invention includes a mode that is placed between the host processor and the external communication network, and that suppresses high power consumption by temporarily stopping operation. To obtain a communication peripheral control device, characterized in that the communication peripheral control device has a function of restarting a temporarily stopped operation in response to reception of valid communication data from the external communication circuit network. .

(Explanation of Examples) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of a system configuration for data communication using the present invention, where l is a host processor, 2 is a 0M08 communication controller, '3 is a modem device, 4 is a clock generation circuit, and 5 is a host processor l and 0M08 communication controller. An interface between communication controllers 2, 6 is a modem device 3
7 is a receiving clock input signal line used for receiving serial data, and 8 is a control clock signal line for controlling the receiving circuit section. , 10 is a control circuit unit that performs control operations for setting and canceling a standby mode for stopping the supply of the system clock signal to the ficMO8 communication controller 2 in response to instructions from the host processor 1. It is.

FIG. 2 is a diagram showing the control circuit section IO in detail, in which a comparison value register 11. A reception shift register 12 that performs a shift operation in response to the rising edge of the reception clock in order to convert serial data received through reception serial data @6 into parallel data. A comparator 1 that compares the values of the comparison value register 11 and the reception shift register 12 according to the falling edge of the reception clock.
3.2 Human-powered AND circuit 14, 15.2 Human-powered NO circuit 1
6,17.0M08 Internal bus 20 in the communication controller 2, output from the comparison value register 11 to which the parallel comparison value used by the comparator 13 is always output) @2
1. An output line 22 of parallel data from the reception shift register which is constantly output to the comparator 13 is shown.

23 is a signal line that is inactive during the standby mode setting period and receives the receiving circuit control clock after the standby mode is released. 24 is a signal line only when the system is set to standby mode by a command from the host processor 1. Become active =!・
The signal line 25 is for setting the pie mode, the signal line 25 becomes active when the reception preparation of the communication controller 2 for 0M08 is completed, and the signal line 26 is for connecting the value of the comparison value register summer 1 and the reception shift register I2. Each signal line is shown to be activated only when the values match.

In this embodiment, the communication protocol is HDLC (High
-Level Data Link Control
), and the comparison value register 11 contains a flag pattern (0
1111110) shall be stored, but in the case of other protocols, 1, for example, in the case of B15ync, 8Y
Various values can be considered to be stored in the comparison value register 11 depending on the communication protocol, such as storing an NC character.

In FIG. 1, the 0M08 communication controller 2 receives commands from the host processor 1 via the interface bus 5, prepares to receive the commands, and when the preparations are completed, the standby mode is set. Next, the standby mode is canceled when the 0M08 communication controller 2 receives the flag pattern (01111110) through the data line 6 to the reception 'J')7.

The above operation will be described in detail with reference to FIG. 2. First, the standby mode is set as follows. In response to a command from the host processor, the signal line 24 for setting standby mode becomes active.
The output of the circuit 17 is inactive. As a result, the output of the two-person AND circuit 14 becomes inactive regardless of the state of the system clock signal line 8, the receiving circuit control clock signal is not applied to the signal line 23, and the 0M08 communication controller No receiving circuit control clock signal is supplied within the receiver circuit. Standby mode is now set.

In the case of this embodiment, preparation for reception is completed before setting the standby mode, the signal line 25 is activated, and the comparison value register 11 receives data from the host processor l to the interface bus 5. It is assumed that a flag pattern (0111111O), which is a value necessary for canceling standby mode, is stored through the internal bus 20.

Next, the standby mode is released as follows. After setting the standby mode, the 0M08 communication controller 2 receives the serial data from the receive serial data line 6.
Data is converted into parallel data by a reception shift register 12 according to the rising edge of the reception clock from the reception clock signal line 7, and then received. This parallel value of the receiving shift register 12 is always outputted from the output line 22, and is synchronized with the flag pattern (01111110) always outputted from the output line 21 of the comparison value register 11 and the falling edge of the receiving clock. It is constantly compared by the comparator 13. If they do not match as a result of this comparison, the output line 26 of the comparator 13 becomes inactive and does not take part in canceling standby mode; however, if they match, the output line 26 of the comparator 13 becomes active and the standby mode is activated. The mode will be canceled. This output line 26 is active, and the signal line 25 indicating the completion of reception preparation is active.
The output of the D circuit 15 is not active, and the two-man power NOR circuit 16
The output of is inactive. Two-man power NO, which is even more inert
Depending on the output of the R circuit 16 and the data on the signal line 24, which is inactive except when setting the standby mode, the output of the 2-way NO input circuit 17 is active, and the data on the receiving circuit control clock signal line 8 is inactive. The receiving circuit control clock signal is transferred to the signal line 23 via the two-man AND circuit 14. The receiving circuit control clock signal is now supplied to the 0M08 communication controller 2, and the standby mode is released.

(Effects of the Invention) As described above, by controlling the clock signal to the 0M08 communication controller 2, power consumption can be reduced even during normal operation, and the power consumption can be controlled from a device other than the host processor. A device with the versatility possible is obtained.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram for data communication using the present invention, and FIG. 2 is a control circuit diagram according to the present invention. l...Host processor, 2...0
M08 Communication controller, 3...Modem device, 4...Clock generation circuit, 5...Interface bus 6...Receiving serial data line, 7 ...Receiving clock signal line, 8...
...Reception circuit control clock signal line, IO...
Control circuit section, 11... Comparison value register, 12.
...Receiving shift register, 13...Comparator, 14...Two-person AND circuit, 15...
...2-man power AND circuit, 16...2 man-power NO
R circuit, 17...Two-man power NOR circuit, 20...
...Internal bus, 2...Output line from the comparison value register, 22...Output line from the J receiving shift register, 23...Inside the CMO8 communication controller a signal line for supplying a receiving circuit control clock signal; 2;
4...Signal line for setting standby mode, 25...Signal line indicating completion of reception preparation, 26
...The output line from the comparator. Agent Patent Attorney Uchihara $7. '、゛。 Jin 1. blade

Claims (1)

[Claims] In a communication peripheral control device that is placed between a host processor and an external communication circuit and has a mode for temporarily stopping internal operations, the control device temporarily suspends internal operation in response to reception of valid communication data from the external communication circuit. 1. A communication peripheral control device, comprising a circuit for restarting an operation that has been temporarily stopped.