JPH07146846A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To provide a multiprocessor system which is capable of reducing power consumption. CONSTITUTION:This multiprocessor is the one where plural processor elements 11 to 14 are controlled by a synchronization control means in the synchronization of the termination of an arithmetic operation and the start of the arithmetic operation. In each processor element 11 to 14, the supply of a clock is started by the arithmetic operation start signal 30 from the synchronization control means, the arithmetic operation in a processor 41 is performed and a clock control means 43 stopping the supply of the clock by arithmetic termination signals 21 to 24 that the processor 41 outputs to the synchronization control means after the arithmetic operation is terminated is provided. As a result, because the supply of the clock is stopped when the processor 41 does not execute the arithmetic operation in its synchronization standby state, power consumption can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to low power consumption of a multiprocessor system.

[0002]

2. Description of the Related Art In a multiprocessor system that performs parallel processing, a barrier synchronization mechanism is used as a hardware synchronization mechanism when each processor executes an operation and once synchronizes to execute the next operation. ing. For example, in the conventional example of the multiprocessor system having the above mechanism,
REPORT OF IEICE, CPSY93-20 (1993-08) ", pages 57 to 64, which are realized by signal line connection between each processor and a synchronization mechanism and a synchronization control circuit.

[0003]

However, in the above-described example, since only the synchronous control of the processor element is performed, the synchronous waiting processor in the state where the operation is completed and waiting for the completion of other processors is almost the same as the operation execution time. No power was consumed and wasted.

Therefore, an object of the present invention is to provide a multiprocessor system capable of reducing power consumption.

[0005]

In order to solve the above problems, a multiprocessor system of the present invention uses a plurality of processor elements and an operation end signal output from each of the processor elements as an input, and all the processor elements are input. A multiprocessor system comprising a synchronization control means for outputting a calculation start signal to all the processor elements after the calculation end signal is inputted from the processor element, wherein the processor element starts a calculation by inputting the calculation start signal. Then, a processor that outputs an operation end signal when the operation ends, a clock generator,
The clock signal generated by the clock generation means is input, the clock signal is output to the processor when the operation start signal is input, and the output of the clock signal is stopped when the operation end signal is input, or And a clock control means for switching to a lower frequency.

[0006]

According to the present invention, with the above-described structure, the synchronization control means outputs the calculation start signal to all the processor elements to start the calculation. In each processor element that has received this operation start signal, the clock control means to which the operation start signal is input supplies the clock generated by the clock generation means to the processor, and the processor starts operation.

When the processor finishes the operation, it outputs an operation end signal, and the clock control means to which the operation end signal is input stops the clock supply to the processor or switches to a lower frequency. Further, the operation end signal output from each processor element is transmitted to the synchronization control means, and the synchronization control means outputs the next operation start signal after the operation end signals are input from all the processor elements. The subsequent operation is similar to the above, and this is repeated.

As described above, while the synchronous control means waits until the operation end signals are input from all the processor elements, the clock supply to the processor which has already completed the operation is stopped, Further, the synchronous control means outputs the operation start signal to the processor, and the clock is supplied to the processor while the processor starts and executes the operation.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A multiprocessor system according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a multiprocessor system according to an embodiment of the present invention, where the number of processors is four. In FIG. 1, 11 to 14 are independent processor elements, 21 to 24 are operation end signal lines for transmitting an operation end signal output by the processor elements after the operation is completed, and 30 is an operation start signal for transmitting an operation start signal to the processor elements. Signal lines 40 are calculation end signal lines 21 to 2 from each processor element.
4 is a synchronization control means for outputting a calculation start signal 30 to each processor element after inputting 4.

FIG. 2 shows the configuration of each processor element in the embodiment of the present invention. Reference numeral 41 is a processor for performing an operation, 42 is a clock generating means for generating and outputting a clock of frequency F, and 43 is a clock controlling means for performing an operation on the clock and transmitting it to the processor.

The operation of the multiprocessor system configured as described above will be described below with reference to FIGS. 1 and 2.

First, when the arithmetic operation is started, the synchronous control means 40 outputs an arithmetic operation start signal to the arithmetic operation start signal line 30 so that each of the processor elements 11-14 starts the arithmetic operation. The signal on the start signal line 30 is also input to the clock control means 43,
The clock control unit 43 supplies the clock signal of the frequency F, which is constantly generated by the clock generation unit 42, to the processor 4
Supply to 1. As a result, each processor 41 operates based on the clock signal generated by the clock generation means 42 and executes an operation.

After that, when each processor finishes the operation, it outputs an operation end signal to the operation end signal lines 21 to 24. At this time, the operation end signal line is the clock control means 43.
The clock control means 43 stops the clock supply to the processor 41. In this way, the operation end signal is output from each of the processor elements 11 to 14, and is output to the synchronization control means 40 through the operation end signal lines 21 to 24. The synchronization control means 40 thus waits for the input of the operation end signal from each of the processor elements 11 to 14, and all the processor elements 1
When the operation end signal is input from 1 to 14, the end of operation is confirmed, and the next operation start signal is sent to the operation start signal line 30.
Output to.

The operation thereafter is the same as that described above, and this is repeated to execute the operation. When the above operation is performed, each processor element 1 is used in normal parallel processing.
Normally, the calculation times in 1 to 14 are different, and before the synchronization control means 40 receives the calculation end signal from all the processor elements 11 to 14, the processor element executing the calculation and the calculation end. Then, both the processor elements in the synchronization wait state exist, but the processor elements in the synchronization wait state are in a state in which the clock supply to the processor is stopped, and the operation start signal is output from the synchronization control means 40. Then, in each processor element, clock supply to the processor is started.

Although the number of processor elements is four in this embodiment, this number may be two or more, and for the operation end signal lines 21 to 24, the processor elements can be specified if the ended processor elements can be specified. No signal lines are needed.

Further, in the present embodiment, the clock control means 43
Although the power consumption is suppressed by disconnecting the clock, the clock frequency may be divided and the frequency may be reduced to supply it to the processor 41.

[0018]

As described above, according to the present invention, it is possible to control the clock supply to the processor by the signal line for synchronous control of the multiprocessor, and to stop the clock of the processor which is not executing the operation in the waiting for synchronization. The clock supply at the time of executing the calculation can be realized by the synchronous control signal.

Therefore, with a simple configuration, it is possible to suppress the power consumption of a processor which is indispensable in a multi-processor system and which is not executing operations in a synchronization waiting state, and the effect increases as the number of processors increases.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a processor element in the same embodiment.

[Explanation of symbols]

 11 processor element 1 12 processor element 2 13 processor element 3 14 processor element 4 21 operation end signal line 1 22 operation end signal line 2 23 operation end signal line 3 24 operation end signal line 4 30 operation start signal line 40 synchronization control means 41 Processor 42 Clock generation means 43 Clock control means

Claims (1)

[Claims] 1. A plurality of processor elements and an operation end signal output from each of the processor elements are input, and after the operation end signals are input from all the processor elements, an operation start signal is sent to all the processor elements. A multiprocessor system having a synchronization control unit for outputting, wherein the processor element starts a calculation by the input of the calculation start signal and outputs a calculation end signal at the end of the calculation, a clock generation unit, The clock signal generated by the clock generation means is input, the clock signal is output to the processor when the operation start signal is input, and the output of the clock signal is stopped or lower when the operation end signal is input. Equipped with clock control means for switching to frequency Multi-processor system.