JPH0553680A - Power controller for computer - Google Patents

Abstract

PURPOSE:To prevent the complexity of the control and to realize the low-power consumption of the device by operating the system by the proper clock according to the operational state of the system. CONSTITUTION:A clock selection circuit 15 switches a selector 19 to a 1MHz oscillator 21 when a processor state signal (p) is in an idle state, an interrupt signal (i) is inputted, and a signal is inputted from a system bus monitoring circuit 17. Then, a clock control part 11 supplies a 1MHz-clock frequency system clock (s) to a processor 1, a main memory 5, and an I/O control part 7. In this case, when the processor 1 executes the process, the clock selection circuit 15 switches the selector 19 to a 10MHz oscillator 23 when an interruption is generated in the I/O control part 7 or when a system bus 3 is used for data transfer. Then the clock control part 11 supplies the 1MHz-clock frequency system clock (s) to the processor 1, main memory 5, and I/O control part 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power control apparatus for a computer which has a logic circuit composed of CMOS and which reduces power consumption.

[0002]

2. Description of the Related Art In recent years, small computers such as personal computers and control devices can be driven with low power consumption such as batteries by reducing the power consumption, and the operation time can be extended to improve the quality of the devices. It is being improved. Further, by reducing the power consumption, the small-sized computer, which was required to be forcedly air-cooled, can be operated by natural air-cooling, which improves the convenience of the apparatus.

In order to achieve the above low power consumption, conventional computers have promoted the low power consumption of components, for example, switching from IC of logic circuits to CMOS. In addition, power consumption is reduced by monitoring the operating condition of the operator on the computer, for example, controlling the clock frequency or operating voltage if the operator does not use the keyboard of the personal computer for a while. A single task operating system such as a personal computer, for example, MS-DOS can reduce power consumption by monitoring the operation status of the operator, but a multitask operating system (hereinafter,
It is called OS. ) Etc., it was not easy to achieve low power consumption.

[0004]

However, since the conventional computer power control apparatus has a plurality of tasks in a multitasking OS or network environment, there is a large amount of data for controlling each task. This leads to complicated control. Further, among the plurality of tasks, if one task is adjusted to the same clock frequency in order to reduce the power consumption of one task, there is a problem that the control of the other task is adversely affected.

The present invention has been made to solve such a conventional problem, and an object thereof is to prevent the control from becoming complicated and to reduce the consumption of the device in a multitasking OS and a network environment. By aiming for electricity,
An object of the present invention is to provide a power control device for a computer that improves the convenience and quality of the device.

[0006]

To achieve the above object, the present invention relates to a power control apparatus for a computer in which the power consumption supplied to the computer is proportional to the clock frequency, and a high clock for supplying the high clock frequency to the computer. Frequency supplying means, low clock frequency supplying means for supplying a low clock frequency to the computer, presence / absence of a bus busy signal of the system bus of the computer, presence / absence of operation of the processor of the computer, and presence / absence of interruption of the computer. A monitoring means for monitoring, a low clock frequency selecting means for selecting the low clock frequency supplying means when the bus busy signal of the computer system bus, the operation of the processor, and the occurrence of an interrupt are not detected by the monitoring means; Bus busy signal of the computer system bus, processor operation and interrupt by means One of the generation is the high clock frequency selection means for selecting the high clock frequency supplying means when the organic, summarized as further comprising a.

[0007]

With the above configuration, the presence / absence of a bus busy signal on the computer system bus, the presence / absence of operation of the processor of the computer, and the presence / absence of interruption of the computer are monitored. This monitoring selects a low clock frequency supply means for supplying a low clock frequency to the computer when there is no bus busy signal on the computer system bus, operation of the processor, and occurrence of an interrupt. On the other hand, when the bus busy signal of the computer system bus, the operation of the processor, or the occurrence of an interrupt is detected by monitoring, the high clock frequency supply means for supplying the high clock frequency to the computer is selected, so that the low power consumption of the device Can be promoted.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the control of an embodiment of a power control system for a computer according to the present invention.

In FIG. 1, the processor 1 controls various processes, and a clock control, which will be described later, gives a processor status signal P indicating a busy status or an idle status of each process by an operating system (hereinafter referred to as OS). Output to the unit 11. In the processor 1 and the like, the power consumption of the logic circuit composed of CMOS is almost proportional to the clock frequency in synchronization with the system clock.

The system bus 3 is a passage for transferring data, control signals and the like by the processor 1 and the like, and when used by the processor 1 and the like, outputs a bus busy signal b to a clock controller 11 which will be described later.

The main memory 5 stores a program indicating the operation of the processor 1 and various data at a predetermined address.

The IO controller 7 controls a peripheral device 9 which will be described later according to a command from the processor 1, and a direct memory access (D) for directly accessing the peripheral device 9 is performed.
(MA) function and the like. The IO control unit 7 generates an interrupt and outputs an interrupt signal i to the processor 1 and a clock control unit 11, which will be described later, when an input / output end signal is input from the peripheral device 9, for example.

The peripheral device 9 is, for example, a magnetic disk device, a display device, a communication control device, etc., and is controlled by the IO control unit 7.

The clock control unit 11 selects the 1 MHZ oscillator 21 or 10 MHZ oscillator 23, which will be described later, in response to the process state signal p input from the processor 1, the bus busy signal b and the interrupt signal i input from the system bus 3. To supply the system clock s to the processor 1, the main memory 5, and the IO control unit 7.

The LAN 13 is connected to the system bus 3 and data is transmitted and received between the terminals.

FIG. 2 is a block diagram showing the control of the clock controller 11 described above.

The clock control section 11 includes a clock selection circuit 15, a system bus monitoring circuit 17, a selector 19,
A 1 MHZ oscillator 21 and a 10 MHZ oscillator 23 are provided.

The clock selection circuit 15 includes a processor status signal p input from the processor 1, an interrupt signal i input from the IO controller 7, and the system bus monitoring circuit 1.
The bus busy signal b input from the selector 7 causes the selector 19
To control. The system bus monitoring circuit 17 outputs a bus busy signal b obtained from the system bus 3 within a fixed time from the system bus 3, for example, when the processor 1 is transferring data using the peripheral device 9 and the system bus 3. To detect. When the bus busy signal b is detected within a fixed time, the system bus monitoring circuit 17 outputs a signal to the clock selection circuit 15.

Here, the fixed time for the system bus monitoring circuit 17 to detect the bus busy signal b from the system bus 3 is different depending on the specifications of the computer.

In the clock selection circuit 15, when the processor state signal p is in the idle state, the interrupt signal i is not input, and the bus busy signal b is not input from the system bus monitoring circuit 17, the selector 19 is set to the 1MHZ oscillator 21. Switch. On the other hand, when the processor status signal p is in the busy state, or the interrupt signal i or the signal from the system bus monitor circuit 17 is input, the clock selection circuit 15 switches the selector 19 to the 10 MHZ oscillator 23.

The clock selection circuit 15 has an AND circuit configuration that takes the logical product of the process state signal p, the interrupt signal i, and the signal from the system bus monitoring circuit 17.

The selector 19 is responsive to the switching control of the clock selection circuit 15 and the 1 MHZ oscillator 21 or 10M.
System clock s of the clock frequency of the HZ oscillator 23
Is output to the processor 1 or the like.

The 1 MHZ oscillator 21 includes a 10 MHZ oscillator 23, which will be described later, in order to reduce power consumption when the processor 1 does not execute any process, the IO controller 7 does not generate an interrupt, and there is no data transfer. The processor 1 and the like are operated at a clock frequency that is a fraction of the highest clock frequency.

The 10 MHZ oscillator 23 is provided in the selector 19 when the processor 1 is executing a process or when the processor 1 is performing data transfer with the peripheral device 9.
To supply the highest clock frequency to the processor 1 and the like.

Next, the operation of this embodiment will be described.

First, after powering on the computer, the clock selection circuit 15 of the clock control unit 11 inputs the interrupt signal i from the IO control unit 7 to the busy state or idle state of the processor state signal p input from the processor 1. And the presence or absence of a signal input from the system bus monitoring circuit 17 are ANDed. When the processor state signal p is in the idle state, the interrupt signal i is input, and the signal is input from the system bus monitoring circuit 17, the clock selection circuit 15 causes the selector 19 to operate the 1 MHZ oscillator 21.
Switch to. When the selector 19 is switched to the 1 MHZ oscillator 19, the clock controller 11 supplies the system clock S having a clock frequency of 1 MHZ to the processor 1, the main memory 5 and the IO controller 7.

When the system clock S having a clock frequency of 1 MHZ is supplied from the 1 MHZ oscillator 21, when the processor 1 executes a process, when an interrupt occurs in the IO controller 7, or when the system bus 3 is used for data transfer. Then, the clock selection circuit 15 operates the selector 1
9 is switched to the 10 MHZ oscillator 23. When the selector 19 is switched to the 10 MHZ oscillator 23, the clock controller 11 causes the processor 1, the main memory 5 and the IO controller 7 to operate.
Is supplied with a system clock s having a clock frequency of 10 MHZ.

As a result, when the processor 1 is not executing a process, for example, when the processor 1 is executing a process, the 1 MHZ oscillator 21 has a power consumption of about 1/10 of the power consumption of the 10 MHZ oscillator 23. By switching to the 10 MHZ oscillator 23 having the highest clock frequency, it is possible to realize low power consumption of the device.

Further, since the device is operated with an appropriate clock in response to the operating status of the processor 1, the system bus 3, etc., it is possible to prevent the control from becoming complicated even in a multitasking OS and network environment.

The present embodiment can be applied to a personal computer, a workstation and various control devices provided with a logic circuit composed of CMOS.

[0032]

As described above, according to the present invention, the system is operated at an appropriate clock in response to the operating status of the system, so that the control is prevented from becoming complicated under the multitasking OS and network environment. By reducing the power consumption of the device, the convenience and quality of the device can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of a power control device for a computer according to the present invention.

FIG. 2 is a block diagram showing control of a clock control unit.

[Explanation of symbols]

 1 Processor 3 System Bus 7 IO Control Unit 11 Clock Control Unit 15 Clock Selection Circuit 17 System Bus Monitoring Circuit 19 Selector 21 1 MHZ Oscillator 23 10 MHZ Oscillator i Interrupt Signal p Processor Status Signal s System Clock

Claims (1)

[Claims] 1. A power control apparatus for a computer, wherein power consumption supplied to the computer is proportional to a clock frequency, and high clock frequency supplying means for supplying a high clock frequency to the computer, and low power for supplying a low clock frequency to the computer. A clock frequency supply means, a monitoring means for monitoring the presence or absence of a bus busy signal on the computer system bus, the presence or absence of operation of the processor of the computer and the occurrence of an interrupt of the computer, and the monitoring means for monitoring the system bus of the computer. A bus busy signal, a processor operation, and a low clock frequency selecting means for selecting the low clock frequency supplying means when an interrupt is not generated; and a bus busy signal of a computer system bus, a processor operation and an interrupt by the monitoring means If any of the occurrences of The power control unit of a computer, characterized by comprising a high clock frequency selection means for selecting the number supplying means.